33 commits

Author	SHA1	Message	Date
Raphael Jacquot	b96dcd717c	cleanups ... pipeline reading from the system ram	2019-03-15 13:50:23 +01:00
Raphael Jacquot	194415a6ed	cleanups	2019-03-15 13:31:37 +01:00
Raphael Jacquot	2d43dc67b7	add the rest of the pointer registers loading instructions	2019-03-15 12:25:47 +01:00
Raphael Jacquot	175c1a48d0	major surgery, add memory read and write back in	2019-03-15 07:15:45 +01:00
Raphael Jacquot	3932d6e1f5	added the code for memory read & write, but it's not enabled yet	2019-03-14 23:07:42 +01:00
Raphael Jacquot	b2ae484450	implement the ALU as it should be	2019-03-14 21:47:05 +01:00
Raphael Jacquot	a533e4ea37	cleanup the startup procedure	2019-03-14 17:52:03 +01:00
Raphael Jacquot	c62d562008	make it so that execution of bus programs happen ... in the same cycle as the instruction modify the way jump and rtn are handled add some registers to the debugger	2019-03-14 16:37:51 +01:00
Raphael Jacquot	5f4a8ca8bd	more fixes	2019-03-14 13:47:09 +01:00
Raphael Jacquot	35823428e7	other verilator fixes	2019-03-14 13:45:14 +01:00
Raphaël Jacquot	f86a1d03c5	implement base alu functionnality	2019-03-06 12:16:34 +01:00
Raphaël Jacquot	f3d1a4d9d4	implement D0=(5)	2019-03-05 06:14:38 +01:00
Raphaël Jacquot	28483afe9a	implement CONFIG and RTN* (0[0-3])	2019-03-05 05:39:34 +01:00
Raphael Jacquot	9168cbc1a2	victory, this works on the fpga \o/ ... using "=" instead of "<=" is evil ! make the fpga halt when necessary	2019-03-04 22:48:09 +01:00
Raphaël Jacquot	479382e004	export rstk_ptr to debugger ... implement LCHEX (and almost done for LAHEX)	2019-03-04 13:28:08 +01:00
Raphaël Jacquot	e47f12f1d7	implement push PC to RSTK	2019-03-04 11:52:05 +01:00
Raphaël Jacquot	908b96df6f	implement CLRHST and variants ... implement SET[HEX|DEC]	2019-03-04 10:53:37 +01:00
Raphaël Jacquot	735504d2b3	implement RESET instruction	2019-03-04 10:15:37 +01:00
Raphaël Jacquot	18a56d750b	export main registers to debugger ... add C register implement C=P n add dumping C register	2019-03-04 09:58:13 +01:00
Raphaël Jacquot	009f01f5d7	implement 8[45]x ST=[01] n ... implement GOVLNG dump 2 lines of registers in debugger now	2019-03-04 08:08:02 +01:00
Raphaël Jacquot	da3cce2c07	execute the first jump successfully, and start reading the next instruction	2019-03-03 22:38:56 +01:00
Raphaël Jacquot	631b7f9153	start implementing jump instructions	2019-03-03 20:48:56 +01:00
Raphaël Jacquot	6dd38500a8	add a counter to slow things down	2019-03-03 15:19:07 +01:00
Raphaël Jacquot	b58be38b10	connect debugger to leds	2019-03-03 13:33:32 +01:00
Raphael Jacquot	7e4ab90369	merge a few wire and assigns... can't do it on port declarations though	2019-03-03 09:47:28 +01:00
Raphael Jacquot	61957fab3e	fix misplaced ifdef ... discover you can directly set contents of a wire without requiring an assign	2019-03-03 09:43:18 +01:00
Raphaël Jacquot	eeb5150159	add the beginnings of a PC and RSTK handler ... fix bad maths in the rom-gx-r module wire in the PC in the debugger and the control unit add an execute flag, to start execution of partially decoded instructions that need reading data from the instruction stream	2019-03-03 09:33:42 +01:00
Raphael Jacquot	21ad359673	fix compiling ... fix the way the bus controller program worked, which generated evil inferred latches	2019-03-02 22:33:58 +01:00
Raphaël Jacquot	2fcd9f7b23	decode our first instruction ... execute said instruction start implementing the debugging engine to see what we are doing	2019-03-02 19:40:31 +01:00
Raphael Jacquot	c5355b4a90	enough was done to start feeding the decoder	2019-03-02 15:52:56 +01:00
Raphael Jacquot	cd2b74dcc8	add some commenting	2019-03-02 15:01:00 +01:00
Raphael Jacquot	3cbd6ac5e1	we are now up to reading the first instruction nibbles	2019-03-02 14:38:01 +01:00
Raphael Jacquot	8ce2d2a993	implement more of the bus controller	2019-03-02 13:22:09 +01:00