mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
160 lines
4.2 KiB
Verilog
160 lines
4.2 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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`include "saturn_def_buscmd.v"
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module saturn_control_unit (
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i_clk,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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i_debug_cycle,
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i_bus_busy,
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o_program_data,
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o_program_address,
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o_no_read,
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i_nibble,
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o_error
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_debug_cycle;
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input wire [0:0] i_bus_busy;
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output reg [4:0] o_program_data;
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output reg [4:0] o_program_address;
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output reg [0:0] o_no_read;
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input wire [3:0] i_nibble;
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output wire [0:0] o_error;
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assign o_error = control_unit_error;
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/**************************************************************************************************
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*
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* cpu modules go here
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*
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*************************************************************************************************/
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/**************************************************************************************************
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*
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* the control unit
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*
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*************************************************************************************************/
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reg [0:0] control_unit_error;
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reg [0:0] just_reset;
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reg [0:0] control_unit_ready;
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reg [4:0] bus_prog_addr;
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initial begin
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o_program_address = 5'd31;
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o_program_data = 5'd0;
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o_no_read = 1'b0;
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control_unit_error = 1'b0;
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just_reset = 1'b1;
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control_unit_ready = 1'b0;
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bus_prog_addr = 5'd0;
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end
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always @(posedge i_clk) begin
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if (!i_debug_cycle && just_reset && i_phases[3]) begin
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/* this happend right after reset */
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`ifdef SIM
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if (!i_reset)
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$display("CTRL %0d: [%d] we are in the control unit", i_phase, i_cycle_ctr);
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`endif
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just_reset <= 1'b0;
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o_program_data <= {1'b1, `BUSCMD_LOAD_PC };
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`ifdef SIM
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$display("CTRL %0d: [%d] pushing LOAD_PC command to pos %d", i_phase, i_cycle_ctr, bus_prog_addr);
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`endif
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/* push the current program pointer out,
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* increment the program pointer
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*/
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o_program_address <= bus_prog_addr;
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bus_prog_addr <= bus_prog_addr + 1;
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end
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/* loop to fill the initial PC value in the program */
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if (!i_debug_cycle && !control_unit_ready && (bus_prog_addr != 5'b0)) begin
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o_program_data <= 5'b0;
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o_program_address <= bus_prog_addr;
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bus_prog_addr <= bus_prog_addr + 1;
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`ifdef SIM
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$write("CTRL %0d: [%d] pushing ADDR[%0d] = 0", i_phase, i_cycle_ctr, bus_prog_addr);
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`endif
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if (bus_prog_addr == 5'd5) begin
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control_unit_ready <= 1'b1;
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`ifdef SIM
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$write(" done");
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`endif
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end
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`ifdef SIM
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$write("\n");
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`endif
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end
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/* this happend otherwise */
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if (!i_debug_cycle && control_unit_ready && !i_bus_busy) begin
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// `ifdef SIM
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// $display("CTRL %0d: [%d] starting to do things", i_phase, i_cycle_ctr);
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// `endif
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if (i_cycle_ctr == 10) begin
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control_unit_error <= 1'b1;
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$display("CTRL %0d: [%d] enough cycles for now", i_phase, i_cycle_ctr);
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end
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if (i_phases[2]) begin
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$display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
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end
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end
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if (i_reset) begin
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o_program_address <= 5'd31;
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o_program_data <= 5'd0;
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o_no_read <= 1'b0;
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control_unit_error <= 1'b0;
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just_reset <= 1'b1;
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control_unit_ready <= 1'b0;
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bus_prog_addr <= 5'd0;
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end
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end
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endmodule
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