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https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
we are now up to reading the first instruction nibbles
This commit is contained in:
Raphael Jacquot
parent
8ce2d2a993
commit
3cbd6ac5e1
2 changed files with 66 additions and 15 deletions
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@ -63,14 +63,20 @@ saturn_control_unit control_unit (
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.i_phase (i_phase),
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.i_cycle_ctr (i_cycle_ctr),
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.i_debug_cycle (dbg_debug_cycle),
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.i_bus_busy (bus_busy),
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.o_program_address (ctrl_unit_prog_addr),
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.o_program_data (ctrl_unit_prog_data),
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.o_no_read (ctrl_unit_no_read),
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.i_nibble (nibble_in),
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.o_error (ctrl_unit_error)
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);
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wire [0:0] ctrl_unit_error;
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wire [4:0] ctrl_unit_prog_addr;
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wire [4:0] ctrl_unit_prog_data;
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wire [0:0] ctrl_unit_no_read;
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/**************************************************************************************************
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*
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@ -101,6 +107,9 @@ assign o_debug_cycle = dbg_debug_cycle;
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*/
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reg [0:0] bus_error;
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reg [0:0] bus_busy;
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reg [3:0] nibble_in;
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/*
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* program list for the bus controller
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* this is used for the control unit to send the bus controller
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@ -108,10 +117,12 @@ reg [0:0] bus_error;
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*/
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reg [4:0] bus_prog_addr;
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reg [4:0] bus_program[0:31];
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reg [4:0] next_bus_prog_addr;
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always @(*) begin
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$write("BUSCTRL %0d: [%d] write prog %d : %5b\n", i_phase, i_cycle_ctr, ctrl_unit_prog_addr, ctrl_unit_prog_data);
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// $write("BUSCTRL0 %0d: [%d] write prog %d : %5b\n", i_phase, i_cycle_ctr, ctrl_unit_prog_addr, ctrl_unit_prog_data);
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bus_program[ctrl_unit_prog_addr] = ctrl_unit_prog_data;
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next_bus_prog_addr = bus_prog_addr + 5'd1;
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end
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/*
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@ -123,6 +134,7 @@ assign o_halt = bus_error || ctrl_unit_error;
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initial begin
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bus_error = 1'b0;
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bus_prog_addr = 5'd31;
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bus_busy = 1'b0;
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end
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/*
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@ -141,13 +153,20 @@ always @(posedge i_clk) begin
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* in this phase, we can send a command or data from the processor
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*/
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if (bus_prog_addr != ctrl_unit_prog_addr) begin
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$write("BUSCTRL %0d: [%d] %d : %5b ", i_phase, i_cycle_ctr, bus_prog_addr + 5'd1, bus_program[bus_prog_addr + 5'd1]);
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if (bus_program[bus_prog_addr + 5'd1][4]) begin
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$write("CMD :");
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$write("BUSCTRL %0d: [%d] %d : %5b ", i_phase, i_cycle_ctr, next_bus_prog_addr, bus_program[next_bus_prog_addr]);
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if (bus_program[next_bus_prog_addr][4]) $write("CMD : ");
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else $write("DATA : ");
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$write("%h\n", bus_program[next_bus_prog_addr][3:0]);
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bus_prog_addr <= next_bus_prog_addr;
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o_bus_is_data <= !bus_program[next_bus_prog_addr][4];
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o_bus_nibble_out <= bus_program[next_bus_prog_addr][3:0];
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o_bus_clk_en <= 1'b1;
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bus_busy <= 1'b1;
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end else begin
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if (!ctrl_unit_no_read) begin
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$display("BUSCTRL %0d: [%d] setting up read", i_phase, i_cycle_ctr);
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o_bus_clk_en <= 1'b1;
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end
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else $write("DATA : %h", bus_program[bus_prog_addr + 5'd1][3:0]);
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$write("\n");
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bus_prog_addr <= bus_prog_addr + 5'd1;
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end
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end
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4'b0010:
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@ -155,12 +174,24 @@ always @(posedge i_clk) begin
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/*
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* this phase is reserved for reading data from the bus
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*/
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if (o_bus_clk_en) begin
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$display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr);
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o_bus_clk_en <= 1'b0;
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if (!ctrl_unit_no_read) begin
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$display("BUSCTRL %0d: [%d] read %h", i_phase, i_cycle_ctr, i_bus_nibble_in);
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nibble_in <= i_bus_nibble_in;
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end
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end
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end
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4'b0100:
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begin
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/*
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* this phase is when the instruction decoder does it's job
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*/
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if ((bus_prog_addr == ctrl_unit_prog_addr) && bus_busy) begin
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$display("BUSCTRL %0d: [%d] done sending the entire program", i_phase, i_cycle_ctr);
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bus_busy <= 1'b0;
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end
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end
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4'b1000:
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begin
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@ -175,6 +206,7 @@ always @(posedge i_clk) begin
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if (i_reset) begin
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bus_error <= 1'b0;
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bus_prog_addr <= 5'd31;
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bus_busy <= 1'b0;
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end
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end
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@ -30,9 +30,14 @@ module saturn_control_unit (
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i_cycle_ctr,
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i_debug_cycle,
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i_bus_busy,
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o_program_data,
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o_program_address,
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o_no_read,
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i_nibble,
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o_error
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);
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@ -43,9 +48,14 @@ input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_debug_cycle;
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input wire [0:0] i_bus_busy;
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output reg [4:0] o_program_data;
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output reg [4:0] o_program_address;
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output reg [0:0] o_no_read;
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input wire [3:0] i_nibble;
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output wire [0:0] o_error;
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assign o_error = control_unit_error;
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@ -70,6 +80,7 @@ reg [4:0] bus_prog_addr;
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initial begin
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o_program_address = 5'd31;
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o_program_data = 5'd0;
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o_no_read = 1'b0;
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control_unit_error = 1'b0;
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just_reset = 1'b1;
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control_unit_ready = 1'b0;
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@ -82,12 +93,12 @@ always @(posedge i_clk) begin
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/* this happend right after reset */
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`ifdef SIM
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if (!i_reset)
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$display("CTRL %0d: [%d] we are in the control unit", i_phase, i_cycle_ctr);
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$display("CTRL %0d: [%d] we are in the control unit", i_phase, i_cycle_ctr);
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`endif
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just_reset <= 1'b0;
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o_program_data <= {1'b1, `BUSCMD_LOAD_PC };
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`ifdef SIM
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$display("CTRL %0d: [%d] pushing LOAD_PC command to pos %d", i_phase, i_cycle_ctr, bus_prog_addr);
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$display("CTRL %0d: [%d] pushing LOAD_PC command to pos %d", i_phase, i_cycle_ctr, bus_prog_addr);
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`endif
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/* push the current program pointer out,
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* increment the program pointer
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@ -102,7 +113,7 @@ always @(posedge i_clk) begin
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o_program_address <= bus_prog_addr;
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bus_prog_addr <= bus_prog_addr + 1;
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`ifdef SIM
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$write("CTRL %0d: [%d] pushing ADDR[%0d] = 0", i_phase, i_cycle_ctr, bus_prog_addr);
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$write("CTRL %0d: [%d] pushing ADDR[%0d] = 0", i_phase, i_cycle_ctr, bus_prog_addr);
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`endif
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if (bus_prog_addr == 5'd5) begin
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control_unit_ready <= 1'b1;
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@ -116,17 +127,25 @@ always @(posedge i_clk) begin
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end
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/* this happend otherwise */
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if (!i_debug_cycle && control_unit_ready) begin
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if (!i_debug_cycle && control_unit_ready && !i_bus_busy) begin
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`ifdef SIM
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$display("CTRL %0d: [%d] starting to do things", i_phase, i_cycle_ctr);
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`endif
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control_unit_error <= 1'b1;
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// `ifdef SIM
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// $display("CTRL %0d: [%d] starting to do things", i_phase, i_cycle_ctr);
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// `endif
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if (i_cycle_ctr == 10) begin
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control_unit_error <= 1'b1;
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$display("CTRL %0d: [%d] enough cycles for now", i_phase, i_cycle_ctr);
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end
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if (i_phases[2]) begin
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$display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
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end
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end
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if (i_reset) begin
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o_program_address <= 5'd31;
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o_program_data <= 5'd0;
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o_no_read <= 1'b0;
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control_unit_error <= 1'b0;
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just_reset <= 1'b1;
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control_unit_ready <= 1'b0;
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