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2019-03-02 14:38:01 +01:00
attic implement the basic rom, and add a few things 2019-02-25 09:17:17 +01:00
.gitignore implement the basic rom, and add a few things 2019-02-25 09:17:17 +01:00
compile add testing for yosys out status 2019-02-12 14:50:13 +01:00
empty_lfe5u-85f.config fix some verilator warnings 2019-02-04 20:36:47 +01:00
gen_rom_hex.py add licence info 2019-02-06 10:40:55 +01:00
ico implement more things, test with ice40 2019-02-10 12:04:53 +01:00
icoboard.pcf implement more things, test with ice40 2019-02-10 12:04:53 +01:00
make_saturn.ESP5.ys starts complete rewrite 2019-02-24 23:30:57 +01:00
make_saturn.ICE40.ys starts complete rewrite 2019-02-24 23:30:57 +01:00
Makefile implement ST=[01] n 2019-02-04 17:00:08 +01:00
README.md cleanup the simulated rom interface 2019-02-18 11:36:28 +01:00
rom-gx-r.hex change the way the rom is encoded, makes things easier 2019-02-04 11:31:58 +01:00
run.sh implement more of the bus controller 2019-03-02 13:22:09 +01:00
saturn_bus.v implement the basic rom, and add a few things 2019-02-25 09:17:17 +01:00
saturn_bus_controller.v we are now up to reading the first instruction nibbles 2019-03-02 14:38:01 +01:00
saturn_control_unit.v we are now up to reading the first instruction nibbles 2019-03-02 14:38:01 +01:00
saturn_debugger.v implement more of the bus controller 2019-03-02 13:22:09 +01:00
saturn_def_buscmd.v implement more of the bus controller 2019-03-02 13:22:09 +01:00
saturn_hp48gx_rom.v implement the basic rom, and add a few things 2019-02-25 09:17:17 +01:00
saturn_top.v implement more of the bus controller 2019-03-02 13:22:09 +01:00
ulx3s_v20.lpf commit more stuff 2019-02-04 17:14:08 +01:00
z_test_rom-1.hex time to start over, this this is broken beyond fiddling 2019-02-24 21:54:15 +01:00
z_test_rom-2.hex time to start over, this this is broken beyond fiddling 2019-02-24 21:54:15 +01:00

Verilog implementation of the HP saturn processor

licence: GPLv3 or later

timings: ___________
reset: |____________________________________________________ ____ ____ ____ ____ ____ ____ clk : | || || || || || |____ _________ _________ _________ _________ _________ counter: /0____X____1____X____2____X____3____X____0 _________ _________ phase_0: | || _________ phase_1: | |____ _________ phase_2: _______________| | _________ phase_3: ___________________________________| |

notes for using the ULX3S

Maybe linux ujprog won't find port because of insufficient priviledge. Either run ujprog as root or have udev rule:# this is for usb-serial tty device SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
MODE="664", GROUP="dialout" this is for ujprog libusb access

ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
GROUP="dialout", MODE="666"