Miroirs/hp-saturn
1
0
Fork 0
mirror of https://github.com/sxpert/hp-saturn synced 2024-09-28 15:20:27 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions

implement more things, test with ice40

Browse source
This commit is contained in:
Raphael Jacquot 2019-02-10 12:04:53 +01:00
parent 4594dec086
commit 23a8e32e31
15 changed files with 127 additions and 10732 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
.gitignore vendored
View file

@ -6,3 +6,6 @@ obj_dir/Vsaturn_core.mk
obj_dir/Vsaturn_core__Syms.cpp
obj_dir/Vsaturn_core__Syms.h
obj_dir/Vsaturn_core_classes.mk
saturn_core.ICE40.json
blinky.pcf
demo.blif

4
decstates.v
View file

@ -25,8 +25,8 @@
`define DEC_GOSUB_LOOP 12'h701 // 7[x] -> exec
`define DEC_8X 12'h800 // 8X
`define DEC_80X 12'h801 // 80X
`define DEC_CONFIG 12'h805 // 805
`define DEC_RESET 12'h80A // 80A
`define DEC_808X 12'h808 // 808X
`define DEC_AC_BIT_SET_TEST 12'h809 // 808[4-B]x
`define DEC_C_EQ_P_N 12'h80C // 80Cn C=P n
`define DEC_P_EQ_C_N 12'h80D // 80Dn P=C n
`define DEC_82X_CLRHST 12'h820 // 82X

10683
demo.blif
View file

File diff suppressed because it is too large Load diff

7
fields.v
View file

@ -1,6 +1,9 @@
`ifndef _FIELDS
`define _FIELDS
`define T_SET 0
`define T_TEST 1
`define T_DIR_OUT 0
`define T_DIR_IN 1
@ -10,6 +13,9 @@
`define T_REG_A 0
`define T_REG_C 1
`define T_FTYPE_FIELD 0
`define T_TTYPE_LEN 1
`define T_FIELD_P 0
`define T_FIELD_WP 1
`define T_FIELD_XS 2
@ -18,7 +24,6 @@
`define T_FIELD_M 5
`define T_FIELD_B 6
`define T_FIELD_W 7
`define T_FIELD_LEN 13
`define T_FIELD_A 15
`endif

3
hp48_02_sys_ram.v
View file

@ -28,7 +28,8 @@ module hp48_sys_ram (
`ifdef SIM
localparam SYS_RAM_LEN = 262144;
`else
localparam SYS_RAM_LEN = 65536;
//localparam SYS_RAM_LEN = 65536;
localparam SYS_RAM_LEN = 2**12;
`endif
reg [0:0] addr_conf;

3
hp48_06_rom.v
View file

@ -27,7 +27,8 @@ localparam ROM_FILENAME = "rom-gx-r.hex";
`ifdef SIM
reg [3:0] rom [0:(2**20)-1];
`else
reg[3:0] rom [0:(2**16)-1];
//reg[3:0] rom [0:(2**16)-1];
reg[3:0] rom [0:(2**12)-1];
`endif
reg [3:0] i_cmd;

1
ico
View file

@ -5,3 +5,4 @@
yosys saturn_core.ICE40.ys
#nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5
nextpnr-ice40 --gui --hx8k --json saturn_core.ICE40.json --pcf-allow-unconstrained --pcf icoboard.pcf --asc saturn_core.ice40.asc

42
icoboard.pcf
View file

@ -27,22 +27,32 @@
# POSSIBILITY OF SUCH DAMAGE.
#
set_io clk_100mhz R9
# set_io clk_100mhz R9
set_io clk_25mhz R9
set_io pmod1_1 D8
set_io pmod1_2 B9
set_io pmod1_3 B10
set_io pmod1_4 B11
set_io pmod1_7 B8
set_io pmod1_8 A9
set_io pmod1_9 A10
set_io pmod1_10 A11
#set_io pmod1_1 D8
#set_io pmod1_2 B9
#set_io pmod1_3 B10
#set_io pmod1_4 B11
#set_io pmod1_7 B8
#set_io pmod1_8 A9
#set_io pmod1_9 A10
#set_io pmod1_10 A11
set_io led[0] D8
set_io led[1] B9
set_io led[2] B10
set_io led[3] B11
set_io led[4] B8
set_io led[5] A9
set_io led[6] A10
set_io led[7] A11
set_io pmod2_7 B7
set_io pmod2_8 B6
set_io pmod2_9 B3
set_io pmod2_10 B5
#set_io pmod2_7 B7
set_io btn[0] B7
#set_io pmod2_8 B6
#set_io pmod2_9 B3
#set_io pmod2_10 B5
set_io rpi_sck H11
set_io rpi_cs D4
set_io rpi_mosi A6
#set_io rpi_sck H11
#set_io rpi_cs D4
#set_io rpi_mosi A6

3
opcodes/13x_ptr_and_AC.v
View file

@ -8,7 +8,8 @@
`DEC_13X: begin
case (nb_in)
4'h5: D1[19:0] = C[19:0];
4'h4: D0[19:0] <= C[19:0];
4'h5: D1[19:0] <= C[19:0];
default: begin
$display("ERROR : DEC_13X");
decode_error <= 1;

52
opcodes/1[45]_memaccess.v
View file

@ -39,25 +39,32 @@
t_cnt <= 1;
t_ctr <= 0;
end
t_ftype <= `T_FTYPE_FIELD;
next_cycle <= `BUSCMD_LOAD_DP;
decstate <= `DEC_MEMAXX;
end else begin
t_ftype <= nb_in[3];
decstate <= `DEC_15X_FIELD;
end
end
`DEC_15X_FIELD: begin
case (nb_in)
4'h0: begin
t_field <= `T_FIELD_P;
t_cnt <= P;
t_ctr <= P;
if (!t_ftype) // fields
case (nb_in)
4'h0: begin
t_field <= `T_FIELD_P;
t_cnt <= P;
t_ctr <= P;
end
default: begin
$display("ERROR : DEC_15X_FIELD");
decode_error <= 1;
end
endcase
else begin
t_cnt = nb_in;
t_ctr = nb_in;
end
default: begin
$display("ERROR : DEC_15X_FIELD");
decode_error <= 1;
end
endcase
next_cycle <= `BUSCMD_LOAD_DP;
decstate <= `DEC_MEMAXX;
end
@ -122,17 +129,18 @@ end
end else begin
$write("DAT%b=%s\t", t_ptr, t_reg?"C":"A");
end
case (t_field)
`T_FIELD_P: $display("P");
`T_FIELD_WP: $display("WP");
`T_FIELD_XS: $display("XS");
`T_FIELD_X: $display("X");
`T_FIELD_S: $display("S");
`T_FIELD_M: $display("M");
`T_FIELD_B: $display("B");
`T_FIELD_W: $display("W");
`T_FIELD_LEN: $display("UNKNOWN");
`T_FIELD_A: $display("A");
endcase
if (!t_ftype)
case (t_field)
`T_FIELD_P: $display("P");
`T_FIELD_WP: $display("WP");
`T_FIELD_XS: $display("XS");
`T_FIELD_X: $display("X");
`T_FIELD_S: $display("S");
`T_FIELD_M: $display("M");
`T_FIELD_B: $display("B");
`T_FIELD_W: $display("W");
`T_FIELD_A: $display("A");
endcase
else $display("%h", t_cnt);
end
end

18
opcodes/808[4-B]_[AC]BIT_set_test.v Normal file
View file

@ -0,0 +1,18 @@
`DEC_AC_BIT_SET_TEST: begin
$display("ERROR: %h | t_reg %b | t_set_test %b | t_set_test_val %b",
nb_in, t_reg, t_set_test, t_set_test_val);
if (!t_set_test) begin
if (!t_reg) A[nb_in] <= t_set_test_val;
else C[nb_in] <= t_set_test_val;
decstate <= `DEC_START;
end else begin
if (!t_reg) Carry <= (A[nb_in] == t_set_test_val);
else Carry <= (C[nb_in] == t_set_test_val);
decstate <= `DEC_TEST_GO;
end
`ifdef SIM
$display("%5h %s%sBIT=%b\t%h",
inst_start_PC, t_set_test?"?":"",
t_reg?"C":"A", t_set_test_val, nb_in);
`endif
end

22
opcodes/808x.v Normal file
View file

@ -0,0 +1,22 @@
/******************************************************************************
* 808x
* a lot of things start with 808x...
*
*/
`include "decstates.v"
`DEC_808X: begin
case (nb_in)
4'h4, 4'h5, 4'h6, 4'h7, 4'h8, 4'h9, 4'hA, 4'hB: begin
t_reg = nb_in[3];
t_set_test = nb_in[1];
t_set_test_val = nb_in[0];
decstate <= `DEC_AC_BIT_SET_TEST;
end
default: begin
$display("ERROR : DEC_808X");
decode_error <= 1;
end
endcase
end

1
opcodes/80x.v
View file

@ -18,6 +18,7 @@
$display("%05h CONFIG", inst_start_PC);
`endif
end
4'h8: decstate <= `DEC_808X;
4'hA: begin
next_cycle <= `BUSCMD_RESET;
decstate <= `DEC_START;

2
saturn_core.ICE40.ys
View file

@ -1,2 +1,2 @@
read_verilog -I. saturn_core.v
synth_ice40 -blif demo.blif
synth_ice40 -top saturn_core -json saturn_core.ICE40.json

15
saturn_core.v
View file

@ -26,15 +26,15 @@ module saturn_core (
`else
module saturn_core (
input clk_25mhz,
input [6:0] btn,
output wifi_gpio0,
input [ 6:0] btn,
// output wifi_gpio0,
output [7:0] led
);
wire clk;
wire reset;
reg clk2;
assign wifi_gpio0 = 1'b1;
// assign wifi_gpio0 = 1'b1;
assign clk = clk_25mhz;
assign reset = btn[1];
@ -108,12 +108,17 @@ reg [3:0] t_ctr;
reg t_dir;
reg t_ptr;
reg t_reg;
reg t_ftype;
reg [3:0] t_field;
reg [3:0] nb_in;
reg [3:0] nb_out;
reg [19:0] add_out;
// temporary stuff
reg t_set_test;
reg t_set_test_val;
// processor registers
reg [19:0] PC;
reg [3:0] P;
@ -326,7 +331,7 @@ always @(posedge ph2)
end
always @(posedge ph3) begin
if (cycle_ctr == 333)
if (cycle_ctr == 390)
debug_stop <= 1;
end
@ -397,6 +402,8 @@ always @(posedge dec_strobe) begin
`include "opcodes/7xxx_GOSUB.v"
`include "opcodes/8x.v"
`include "opcodes/80x.v"
`include "opcodes/808x.v"
`include "opcodes/808[4-B]_[AC]BIT_set_test.v"
`include "opcodes/80[CD]n_C_and_P_n.v"
`include "opcodes/82x_CLRHST.v"
`include "opcodes/8[4567]n_work_test_ST.v"