mirror of
https://github.com/sxpert/hp-saturn
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32 lines
680 B
Verilog
32 lines
680 B
Verilog
/******************************************************************************
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* 13X
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*
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*
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*/
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`include "decstates.v"
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`DEC_13X: begin
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case (nb_in)
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4'h4: D0[19:0] <= C[19:0];
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4'h5: D1[19:0] <= C[19:0];
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default: begin
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$display("ERROR : DEC_13X");
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decode_error <= 1;
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end
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endcase
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decstate <= `DEC_START;
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`ifdef SIM
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$write("%5h ", inst_start_PC);
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if (!nb_in[1])
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$write("D");
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else
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$write("%sD", nb_in[3]?"C":"A");
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$write("%b", nb_in[0]);
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if (!nb_in[1])
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$write("=%s%s", nb_in[2]?"C":"A", nb_in[3]?"S":"");
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else
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$write("%s", nb_in[3]?"XS":"EX");
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$display("");
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`endif
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end
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