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63 commits 1 branch 0 tags 2 MiB
Verilog 99%
Shell 0.7%
Makefile 0.2%
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Raphael Jacquot 23a8e32e31 implement more things, test with ice40
2019-02-10 12:04:53 +01:00
opcodes implement more things, test with ice40 2019-02-10 12:04:53 +01:00
.gitignore implement more things, test with ice40 2019-02-10 12:04:53 +01:00
bus_commands.v rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
compile try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
decstates.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
empty_lfe5u-85f.config fix some verilator warnings 2019-02-04 20:36:47 +01:00
fields.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
gen_rom_hex.py add licence info 2019-02-06 10:40:55 +01:00
gxrom-r-decompile implement ST=[01] n 2019-02-04 17:00:08 +01:00
hp48_00_bus.v bus access all rewritten 2019-02-09 09:32:29 +01:00
hp48_01_io_ram.v add more stuff 2019-02-09 11:53:45 +01:00
hp48_02_sys_ram.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
hp48_06_rom.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
ico implement more things, test with ice40 2019-02-10 12:04:53 +01:00
icoboard.pcf implement more things, test with ice40 2019-02-10 12:04:53 +01:00
Makefile implement ST=[01] n 2019-02-04 17:00:08 +01:00
README separate reading instructions from reading data 2019-02-07 08:35:59 +01:00
rom-gx-r.hex change the way the rom is encoded, makes things easier 2019-02-04 11:31:58 +01:00
run rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
saturn_core.ESP5.ys try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
saturn_core.ICE40.ys implement more things, test with ice40 2019-02-10 12:04:53 +01:00
saturn_core.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
text.vcd implement ST=[01] n 2019-02-04 17:00:08 +01:00
ulx3s_v20.lpf commit more stuff 2019-02-04 17:14:08 +01:00

README 

Verilog implementation of the HP saturn processor

licence: GPLv3 or later


timings:

read:
                ____      ____      ____      ____      ____
clk :      ____|    |____|    |____|    |____|    |____|    |____
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address:   ____|         |_______________________________________
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data:      _________|         |__________________________________
                          
read:      ______________|_______________________________________