mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-26 09:58:09 +01:00
bus access all rewritten
This commit is contained in:
parent
c0e4c0b20c
commit
8ae31087eb
4 changed files with 177 additions and 68 deletions
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@ -1,9 +1,19 @@
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`define MMIO
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`define SYSRAM
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`include "bus_commands.v"
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`ifdef MMIO
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`include "hp48_01_io_ram.v"
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`endif
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`ifdef SYSRAM
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`include "hp48_02_sys_ram.v"
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`endif
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`include "hp48_06_rom.v"
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`ifndef _HP48_BUS
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`define _HP48_BUS
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@ -21,8 +31,8 @@ module hp48_bus (
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input [19:0] address,
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input [3:0] command,
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input [3:0] nibble_in,
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output reg [3:0] nibble_out,
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output reg bus_error
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output [3:0] nibble_out,
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output bus_error
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);
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// mmio
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@ -44,6 +54,9 @@ wire sysram_error;
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// rom
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wire [3:0] rom_nibble_out;
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`ifdef MMIO
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//
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// listed in order of priority
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//
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@ -63,6 +76,17 @@ hp48_io_ram dev_io_ram (
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assign mmio_nibble_in = nibble_in;
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assign mmio_daisy_in = 1;
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`else
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assign mmio_error = 0;
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assign mmio_active = 0;
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assign mmio_nibble_out = 0;
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assign mmio_error = 0;
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`endif
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`ifdef SYSRAM
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hp48_sys_ram dev_sys_ram (
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.strobe (strobe),
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.reset (reset),
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@ -79,6 +103,13 @@ hp48_sys_ram dev_sys_ram (
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assign sysram_nibble_in = nibble_in;
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assign sysram_daisy_in = mmio_daisy_out;
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`else
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assign sysram_active = 0;
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assign sysram_nibble_out = 0;
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assign sysram_error = 0;
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`endif
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hp48_rom dev_rom (
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.strobe (strobe),
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@ -88,13 +119,29 @@ hp48_rom dev_rom (
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);
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always @(*)
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begin
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bus_error = mmio_error;
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if (strobe & mmio_active) nibble_out = mmio_nibble_out;
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if (strobe & (!mmio_active & sysram_active)) nibble_out = sysram_nibble_out;
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if (strobe & (!mmio_active & !sysram_active)) nibble_out = rom_nibble_out;
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end
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assign bus_error = mmio_error | sysram_error;
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wire show_mmio;
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wire show_sysram;
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wire show_rom;
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assign show_mmio = mmio_active;
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assign show_sysram = !mmio_active & sysram_active;
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assign show_rom = !mmio_active & !sysram_active;
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assign nibble_out = {4 {strobe}} & (
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({4 {show_mmio}} & mmio_nibble_out) |
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({4 {show_sysram}} & sysram_nibble_out) |
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({4 {show_rom}} & rom_nibble_out));
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// initial begin
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// $monitor("BUS > STRB %b | MMIO %b %h | SYSRAM %b %h | ROM %b %h | IN %h | OUT %h",
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// strobe,
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// show_mmio, mmio_nibble_out,
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// show_sysram, sysram_nibble_out,
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// show_rom, rom_nibble_out,
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// nibble_in, nibble_out);
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// end
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endmodule
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@ -19,7 +19,7 @@ module hp48_io_ram (
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input [3:0] command,
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input [3:0] nibble_in,
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output reg [3:0] nibble_out,
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output reg active,
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output active,
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input daisy_in,
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output daisy_out,
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output reg error
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@ -74,6 +74,10 @@ initial
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$write("\n");
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$display("io_ram: initialized");
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`endif
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// $monitor("MMIO MON | PC %h | DP %h | P %h | A %h | B %h | L %h | CNF %b | RD %b | WR %b | ACT %b",
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// pc_ptr, dp_ptr, ptr_value, access_addr, base_addr, last_addr,
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// configured, can_read, can_write, active);
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end
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/*
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@ -87,44 +91,80 @@ wire cmd_write;
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assign cmd_bus_pc = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_PC_WRITE);
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assign cmd_bus_dp = (command == `BUSCMD_DP_READ) | (command == `BUSCMD_DP_WRITE);
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assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_WRITE);
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assign cmd_write = (command == `BUSCMD_DP_WRITE) | (command == `BUSCMD_PC_WRITE);
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assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_READ);
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assign cmd_write = (command == `BUSCMD_PC_WRITE) | (command == `BUSCMD_DP_WRITE);
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always @(*)
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begin
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active = 0;
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wire [19:0] last_addr;
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if ((command==`BUSCMD_PC_READ)|(command==`BUSCMD_PC_WRITE))
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active = ((base_addr>=pc_ptr)&(pc_ptr<base_addr+IO_RAM_LEN))&(configured);
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if ((command==`BUSCMD_DP_READ)|(command==`BUSCMD_DP_WRITE))
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active = ((base_addr>=dp_ptr)&(dp_ptr<base_addr+IO_RAM_LEN))&(configured);
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end
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assign last_addr = base_addr + IO_RAM_LEN - 1;
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wire pc_lower;
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wire pc_higher;
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wire use_pc;
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wire dp_lower;
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wire dp_higher;
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wire use_dp;
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assign pc_lower = pc_ptr < base_addr;
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assign pc_higher = pc_ptr > last_addr;
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assign use_pc = !(pc_lower | pc_higher);
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assign dp_lower = dp_ptr < base_addr;
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assign dp_higher = dp_ptr > last_addr;
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assign use_dp = !(dp_lower | dp_higher);
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wire [19:0] ptr_value;
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wire [19:0] access_addr;
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assign ptr_value = (cmd_bus_dp?dp_ptr:pc_ptr);
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assign access_addr = ptr_value - base_addr;
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wire read_pc;
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wire write_pc;
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wire read_dp;
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wire write_dp;
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assign read_pc = use_pc & cmd_bus_pc & cmd_read;
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assign write_pc = use_pc & cmd_bus_pc & cmd_write;
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assign read_dp = use_dp & cmd_bus_dp & cmd_read;
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assign write_dp = use_dp & cmd_bus_dp & cmd_write;
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wire can_read;
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wire can_write;
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assign can_read = configured & (read_pc | read_dp);
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assign can_write = configured & (write_pc | write_dp);
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assign active = can_read | can_write;
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always @(posedge strobe) begin
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// read from ram
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if (configured & cmd_read)
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nibble_out <= mmio_ram[(cmd_bus_dp?dp_ptr:pc_ptr) - base_addr];
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if (can_read) begin
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nibble_out = mmio_ram[access_addr];
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end
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end
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always @(posedge strobe) begin
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// write to ram
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if (configured & cmd_write)
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mmio_ram[(cmd_bus_dp?dp_ptr:pc_ptr) - base_addr] <= nibble_in;
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if (can_write) begin
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mmio_ram[access_addr] <= nibble_in;
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end
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end
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always @(posedge strobe) begin
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case (command)
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`BUSCMD_PC_READ: begin
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pc_ptr <= pc_ptr + 1;
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$display("MMIO (%b - %5h) ACT %b - %s_PC %5h (%5h) -> %h",
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configured, base_addr, active,
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cmd_read?"READ":"WRITE", ptr_value, access_addr,
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cmd_read?nibble_out:nibble_in);
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end
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`BUSCMD_DP_READ, `BUSCMD_DP_WRITE: begin
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dp_ptr <= dp_ptr + 1;
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$display("MMIO (%b - %5h) ACT %b - %s_DP %5h (%5h) -> %h",
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configured, base_addr, active,
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cmd_read?"READ":"WRITE", ptr_value, access_addr,
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cmd_read?nibble_out:nibble_in);
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end
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`BUSCMD_LOAD_PC: begin
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// $display("MMIO (%b - %5h) - LOAD_PC %5h", configured, base_addr, address);
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@ -35,7 +35,6 @@ reg [0:0] addr_conf;
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reg [0:0] len_conf;
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reg [19:0] base_addr;
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reg [19:0] length;
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reg [19:0] last_addr;
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reg [19:0] pc_ptr;
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reg [19:0] dp_ptr;
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reg [3:0] sys_ram [0:SYS_RAM_LEN - 1];
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*
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*/
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// PC_PTR tests
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wire cmd_bus_pc;
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wire [19:0] b_addr_minus_pc_ptr;
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wire b_addr_infeq_pc_ptr;
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wire [19:0] pc_ptr_minus_l_addr;
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wire pc_ptr_inf_l_addr;
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wire active_pc_ptr;
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assign cmd_bus_pc = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_PC_WRITE);
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assign {b_addr_infeq_pc_ptr, b_addr_minus_pc_ptr} = base_addr - pc_ptr - 1;
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assign {pc_ptr_inf_l_addr, pc_ptr_minus_l_addr} = pc_ptr - last_addr - 1;
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assign active_pc_ptr = cmd_bus_pc & b_addr_infeq_pc_ptr & pc_ptr_inf_l_addr;
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// PC_PTR tests
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wire cmd_bus_dp;
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wire [19:0] b_addr_minus_dp_ptr;
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wire b_addr_infeq_dp_ptr;
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wire [19:0] dp_ptr_minus_l_addr;
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wire dp_ptr_inf_l_addr;
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wire active_dp_ptr;
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assign cmd_bus_dp = (command == `BUSCMD_DP_READ) | (command == `BUSCMD_DP_WRITE);
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assign {b_addr_infeq_dp_ptr, b_addr_minus_dp_ptr} = base_addr - dp_ptr - 1;
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assign {dp_ptr_inf_l_addr, dp_ptr_minus_l_addr} = dp_ptr - last_addr - 1;
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assign active_dp_ptr = cmd_bus_dp & b_addr_infeq_dp_ptr & dp_ptr_inf_l_addr;
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// global
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wire cmd_read;
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wire cmd_write;
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assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_WRITE);
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assign cmd_write = (command == `BUSCMD_DP_WRITE) | (command == `BUSCMD_PC_WRITE);
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assign cmd_bus_pc = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_PC_WRITE);
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assign cmd_bus_dp = (command == `BUSCMD_DP_READ) | (command == `BUSCMD_DP_WRITE);
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assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_READ);
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assign cmd_write = (command == `BUSCMD_PC_WRITE) | (command == `BUSCMD_DP_WRITE);
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wire [19:0] last_addr;
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assign last_addr = base_addr + length - 1;
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wire pc_lower;
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wire pc_higher;
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wire use_pc;
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wire dp_lower;
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wire dp_higher;
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wire use_dp;
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assign pc_lower = pc_ptr < base_addr;
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assign pc_higher = pc_ptr > last_addr;
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assign use_pc = !(pc_lower | pc_higher);
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assign dp_lower = dp_ptr < base_addr;
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assign dp_higher = dp_ptr > last_addr;
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assign use_dp = !(dp_lower | dp_higher);
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wire [19:0] ptr_value;
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wire [19:0] access_addr;
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assign ptr_value = (cmd_bus_dp?dp_ptr:pc_ptr);
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assign access_addr = ptr_value - base_addr;
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wire read_pc;
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wire write_pc;
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wire read_dp;
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wire write_dp;
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assign read_pc = use_pc & cmd_bus_pc & cmd_read;
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assign write_pc = use_pc & cmd_bus_pc & cmd_write;
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assign read_dp = use_dp & cmd_bus_dp & cmd_read;
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assign write_dp = use_dp & cmd_bus_dp & cmd_write;
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wire can_read;
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wire can_write;
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assign can_read = configured & (read_pc | read_dp);
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assign can_write = configured & (write_pc | write_dp);
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assign active = can_read | can_write;
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assign active = (active_pc_ptr | active_dp_ptr) & configured;
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always @(posedge strobe) begin
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// read from ram
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if (configured & cmd_read)
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nibble_out <= sys_ram[(cmd_bus_dp?dp_ptr:pc_ptr) - base_addr];
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if (can_read) begin
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nibble_out = sys_ram[access_addr];
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end
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end
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always @(posedge strobe) begin
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// write to ram
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if (configured & cmd_write)
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sys_ram[(cmd_bus_dp?dp_ptr:pc_ptr) - base_addr] <= nibble_in;
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if (can_write) begin
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sys_ram[access_addr] <= nibble_in;
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end
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end
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always @(posedge strobe) begin
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case (command)
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`BUSCMD_PC_READ, `BUSCMD_PC_WRITE: begin
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pc_ptr <= pc_ptr + 1;
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// $display("SYSRAM (%b - %5h %5h) ACT %b - %s_PC %5h (%5h) -> %h",
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// configured, base_addr, last_addr, active,
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// cmd_read?"READ":"WRITE", ptr_value, access_addr,
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// cmd_read?nibble_out:nibble_in);
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end
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`BUSCMD_DP_READ, `BUSCMD_DP_WRITE: begin
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dp_ptr <= dp_ptr + 1;
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// $display("SYSRAM (%b - %5h %5h) ACT %b - %s_DP %5h (%5h) -> %h",
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// configured, base_addr, last_addr, active,
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// cmd_read?"READ":"WRITE", ptr_value, access_addr,
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// cmd_read?nibble_out:nibble_in);
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end
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`BUSCMD_LOAD_PC: begin
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pc_ptr <= address;
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if (len_conf & !addr_conf) begin
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base_addr <= address;
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addr_conf <= 1;
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last_addr <= address + length - 1;
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$display("SYSRAM (%b - %5h %5h) - CONFIGURE ADDRESS %5h", configured, address, length, address);
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end
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end else begin
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@ -318,7 +318,7 @@ always @(posedge ph2)
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end
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always @(posedge ph3) begin
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if (cycle_ctr == 145)
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if (cycle_ctr == 150)
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debug_stop <= 1;
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end
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