bus access all rewritten

This commit is contained in:
Raphael Jacquot 2019-02-09 09:32:29 +01:00
parent c0e4c0b20c
commit 8ae31087eb
4 changed files with 177 additions and 68 deletions

View file

@ -1,9 +1,19 @@
`define MMIO
`define SYSRAM
`include "bus_commands.v"
`ifdef MMIO
`include "hp48_01_io_ram.v"
`endif
`ifdef SYSRAM
`include "hp48_02_sys_ram.v"
`endif
`include "hp48_06_rom.v"
`ifndef _HP48_BUS
`define _HP48_BUS
@ -21,8 +31,8 @@ module hp48_bus (
input [19:0] address,
input [3:0] command,
input [3:0] nibble_in,
output reg [3:0] nibble_out,
output reg bus_error
output [3:0] nibble_out,
output bus_error
);
// mmio
@ -44,6 +54,9 @@ wire sysram_error;
// rom
wire [3:0] rom_nibble_out;
`ifdef MMIO
//
// listed in order of priority
//
@ -63,6 +76,17 @@ hp48_io_ram dev_io_ram (
assign mmio_nibble_in = nibble_in;
assign mmio_daisy_in = 1;
`else
assign mmio_error = 0;
assign mmio_active = 0;
assign mmio_nibble_out = 0;
assign mmio_error = 0;
`endif
`ifdef SYSRAM
hp48_sys_ram dev_sys_ram (
.strobe (strobe),
.reset (reset),
@ -79,6 +103,13 @@ hp48_sys_ram dev_sys_ram (
assign sysram_nibble_in = nibble_in;
assign sysram_daisy_in = mmio_daisy_out;
`else
assign sysram_active = 0;
assign sysram_nibble_out = 0;
assign sysram_error = 0;
`endif
hp48_rom dev_rom (
.strobe (strobe),
@ -88,13 +119,29 @@ hp48_rom dev_rom (
);
always @(*)
begin
bus_error = mmio_error;
if (strobe & mmio_active) nibble_out = mmio_nibble_out;
if (strobe & (!mmio_active & sysram_active)) nibble_out = sysram_nibble_out;
if (strobe & (!mmio_active & !sysram_active)) nibble_out = rom_nibble_out;
end
assign bus_error = mmio_error | sysram_error;
wire show_mmio;
wire show_sysram;
wire show_rom;
assign show_mmio = mmio_active;
assign show_sysram = !mmio_active & sysram_active;
assign show_rom = !mmio_active & !sysram_active;
assign nibble_out = {4 {strobe}} & (
({4 {show_mmio}} & mmio_nibble_out) |
({4 {show_sysram}} & sysram_nibble_out) |
({4 {show_rom}} & rom_nibble_out));
// initial begin
// $monitor("BUS > STRB %b | MMIO %b %h | SYSRAM %b %h | ROM %b %h | IN %h | OUT %h",
// strobe,
// show_mmio, mmio_nibble_out,
// show_sysram, sysram_nibble_out,
// show_rom, rom_nibble_out,
// nibble_in, nibble_out);
// end
endmodule

View file

@ -19,7 +19,7 @@ module hp48_io_ram (
input [3:0] command,
input [3:0] nibble_in,
output reg [3:0] nibble_out,
output reg active,
output active,
input daisy_in,
output daisy_out,
output reg error
@ -74,6 +74,10 @@ initial
$write("\n");
$display("io_ram: initialized");
`endif
// $monitor("MMIO MON | PC %h | DP %h | P %h | A %h | B %h | L %h | CNF %b | RD %b | WR %b | ACT %b",
// pc_ptr, dp_ptr, ptr_value, access_addr, base_addr, last_addr,
// configured, can_read, can_write, active);
end
/*
@ -87,44 +91,80 @@ wire cmd_write;
assign cmd_bus_pc = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_PC_WRITE);
assign cmd_bus_dp = (command == `BUSCMD_DP_READ) | (command == `BUSCMD_DP_WRITE);
assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_WRITE);
assign cmd_write = (command == `BUSCMD_DP_WRITE) | (command == `BUSCMD_PC_WRITE);
assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_READ);
assign cmd_write = (command == `BUSCMD_PC_WRITE) | (command == `BUSCMD_DP_WRITE);
always @(*)
begin
active = 0;
wire [19:0] last_addr;
if ((command==`BUSCMD_PC_READ)|(command==`BUSCMD_PC_WRITE))
active = ((base_addr>=pc_ptr)&(pc_ptr<base_addr+IO_RAM_LEN))&(configured);
if ((command==`BUSCMD_DP_READ)|(command==`BUSCMD_DP_WRITE))
active = ((base_addr>=dp_ptr)&(dp_ptr<base_addr+IO_RAM_LEN))&(configured);
end
assign last_addr = base_addr + IO_RAM_LEN - 1;
wire pc_lower;
wire pc_higher;
wire use_pc;
wire dp_lower;
wire dp_higher;
wire use_dp;
assign pc_lower = pc_ptr < base_addr;
assign pc_higher = pc_ptr > last_addr;
assign use_pc = !(pc_lower | pc_higher);
assign dp_lower = dp_ptr < base_addr;
assign dp_higher = dp_ptr > last_addr;
assign use_dp = !(dp_lower | dp_higher);
wire [19:0] ptr_value;
wire [19:0] access_addr;
assign ptr_value = (cmd_bus_dp?dp_ptr:pc_ptr);
assign access_addr = ptr_value - base_addr;
wire read_pc;
wire write_pc;
wire read_dp;
wire write_dp;
assign read_pc = use_pc & cmd_bus_pc & cmd_read;
assign write_pc = use_pc & cmd_bus_pc & cmd_write;
assign read_dp = use_dp & cmd_bus_dp & cmd_read;
assign write_dp = use_dp & cmd_bus_dp & cmd_write;
wire can_read;
wire can_write;
assign can_read = configured & (read_pc | read_dp);
assign can_write = configured & (write_pc | write_dp);
assign active = can_read | can_write;
always @(posedge strobe) begin
// read from ram
if (configured & cmd_read)
nibble_out <= mmio_ram[(cmd_bus_dp?dp_ptr:pc_ptr) - base_addr];
if (can_read) begin
nibble_out = mmio_ram[access_addr];
end
end
always @(posedge strobe) begin
// write to ram
if (configured & cmd_write)
mmio_ram[(cmd_bus_dp?dp_ptr:pc_ptr) - base_addr] <= nibble_in;
if (can_write) begin
mmio_ram[access_addr] <= nibble_in;
end
end
always @(posedge strobe) begin
case (command)
`BUSCMD_PC_READ: begin
pc_ptr <= pc_ptr + 1;
$display("MMIO (%b - %5h) ACT %b - %s_PC %5h (%5h) -> %h",
configured, base_addr, active,
cmd_read?"READ":"WRITE", ptr_value, access_addr,
cmd_read?nibble_out:nibble_in);
end
`BUSCMD_DP_READ, `BUSCMD_DP_WRITE: begin
dp_ptr <= dp_ptr + 1;
$display("MMIO (%b - %5h) ACT %b - %s_DP %5h (%5h) -> %h",
configured, base_addr, active,
cmd_read?"READ":"WRITE", ptr_value, access_addr,
cmd_read?nibble_out:nibble_in);
end
`BUSCMD_LOAD_PC: begin
// $display("MMIO (%b - %5h) - LOAD_PC %5h", configured, base_addr, address);

View file

@ -35,7 +35,6 @@ reg [0:0] addr_conf;
reg [0:0] len_conf;
reg [19:0] base_addr;
reg [19:0] length;
reg [19:0] last_addr;
reg [19:0] pc_ptr;
reg [19:0] dp_ptr;
reg [3:0] sys_ram [0:SYS_RAM_LEN - 1];
@ -89,65 +88,89 @@ initial
*
*/
// PC_PTR tests
wire cmd_bus_pc;
wire [19:0] b_addr_minus_pc_ptr;
wire b_addr_infeq_pc_ptr;
wire [19:0] pc_ptr_minus_l_addr;
wire pc_ptr_inf_l_addr;
wire active_pc_ptr;
assign cmd_bus_pc = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_PC_WRITE);
assign {b_addr_infeq_pc_ptr, b_addr_minus_pc_ptr} = base_addr - pc_ptr - 1;
assign {pc_ptr_inf_l_addr, pc_ptr_minus_l_addr} = pc_ptr - last_addr - 1;
assign active_pc_ptr = cmd_bus_pc & b_addr_infeq_pc_ptr & pc_ptr_inf_l_addr;
// PC_PTR tests
wire cmd_bus_dp;
wire [19:0] b_addr_minus_dp_ptr;
wire b_addr_infeq_dp_ptr;
wire [19:0] dp_ptr_minus_l_addr;
wire dp_ptr_inf_l_addr;
wire active_dp_ptr;
assign cmd_bus_dp = (command == `BUSCMD_DP_READ) | (command == `BUSCMD_DP_WRITE);
assign {b_addr_infeq_dp_ptr, b_addr_minus_dp_ptr} = base_addr - dp_ptr - 1;
assign {dp_ptr_inf_l_addr, dp_ptr_minus_l_addr} = dp_ptr - last_addr - 1;
assign active_dp_ptr = cmd_bus_dp & b_addr_infeq_dp_ptr & dp_ptr_inf_l_addr;
// global
wire cmd_read;
wire cmd_write;
assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_WRITE);
assign cmd_write = (command == `BUSCMD_DP_WRITE) | (command == `BUSCMD_PC_WRITE);
assign cmd_bus_pc = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_PC_WRITE);
assign cmd_bus_dp = (command == `BUSCMD_DP_READ) | (command == `BUSCMD_DP_WRITE);
assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_READ);
assign cmd_write = (command == `BUSCMD_PC_WRITE) | (command == `BUSCMD_DP_WRITE);
wire [19:0] last_addr;
assign last_addr = base_addr + length - 1;
wire pc_lower;
wire pc_higher;
wire use_pc;
wire dp_lower;
wire dp_higher;
wire use_dp;
assign pc_lower = pc_ptr < base_addr;
assign pc_higher = pc_ptr > last_addr;
assign use_pc = !(pc_lower | pc_higher);
assign dp_lower = dp_ptr < base_addr;
assign dp_higher = dp_ptr > last_addr;
assign use_dp = !(dp_lower | dp_higher);
wire [19:0] ptr_value;
wire [19:0] access_addr;
assign ptr_value = (cmd_bus_dp?dp_ptr:pc_ptr);
assign access_addr = ptr_value - base_addr;
wire read_pc;
wire write_pc;
wire read_dp;
wire write_dp;
assign read_pc = use_pc & cmd_bus_pc & cmd_read;
assign write_pc = use_pc & cmd_bus_pc & cmd_write;
assign read_dp = use_dp & cmd_bus_dp & cmd_read;
assign write_dp = use_dp & cmd_bus_dp & cmd_write;
wire can_read;
wire can_write;
assign can_read = configured & (read_pc | read_dp);
assign can_write = configured & (write_pc | write_dp);
assign active = can_read | can_write;
assign active = (active_pc_ptr | active_dp_ptr) & configured;
always @(posedge strobe) begin
// read from ram
if (configured & cmd_read)
nibble_out <= sys_ram[(cmd_bus_dp?dp_ptr:pc_ptr) - base_addr];
if (can_read) begin
nibble_out = sys_ram[access_addr];
end
end
always @(posedge strobe) begin
// write to ram
if (configured & cmd_write)
sys_ram[(cmd_bus_dp?dp_ptr:pc_ptr) - base_addr] <= nibble_in;
if (can_write) begin
sys_ram[access_addr] <= nibble_in;
end
end
always @(posedge strobe) begin
case (command)
`BUSCMD_PC_READ, `BUSCMD_PC_WRITE: begin
pc_ptr <= pc_ptr + 1;
// $display("SYSRAM (%b - %5h %5h) ACT %b - %s_PC %5h (%5h) -> %h",
// configured, base_addr, last_addr, active,
// cmd_read?"READ":"WRITE", ptr_value, access_addr,
// cmd_read?nibble_out:nibble_in);
end
`BUSCMD_DP_READ, `BUSCMD_DP_WRITE: begin
dp_ptr <= dp_ptr + 1;
// $display("SYSRAM (%b - %5h %5h) ACT %b - %s_DP %5h (%5h) -> %h",
// configured, base_addr, last_addr, active,
// cmd_read?"READ":"WRITE", ptr_value, access_addr,
// cmd_read?nibble_out:nibble_in);
end
`BUSCMD_LOAD_PC: begin
pc_ptr <= address;
@ -168,7 +191,6 @@ always @(posedge strobe) begin
if (len_conf & !addr_conf) begin
base_addr <= address;
addr_conf <= 1;
last_addr <= address + length - 1;
$display("SYSRAM (%b - %5h %5h) - CONFIGURE ADDRESS %5h", configured, address, length, address);
end
end else begin

View file

@ -318,7 +318,7 @@ always @(posedge ph2)
end
always @(posedge ph3) begin
if (cycle_ctr == 145)
if (cycle_ctr == 150)
debug_stop <= 1;
end