mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-24 21:59:33 +01:00
added the code for memory read & write, but it's not enabled yet
This commit is contained in:
Raphael Jacquot
parent
a1b22269b2
commit
3932d6e1f5
1 changed files with 137 additions and 21 deletions
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@ -484,9 +484,9 @@ always @(posedge i_clk) begin
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*
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*/
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if (i_clk_en && control_unit_ready && !i_bus_busy) begin
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if (i_clk_en && control_unit_ready) begin
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if (i_phases[3] && dec_instr_execute) begin
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if (i_phases[3] && !i_bus_busy && dec_instr_execute) begin
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case (dec_instr_type)
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`INSTR_TYPE_NOP: begin
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$display("CTRL %0d: [%d] NOP instruction", i_phase, i_cycle_ctr);
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@ -609,6 +609,24 @@ always @(posedge i_clk) begin
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end
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endcase
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end
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// `INSTR_TYPE_MEM_READ:
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// begin
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// $display("CTRL %0d: [%d] MEM READ", i_phase, i_cycle_ctr);
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// bus_program[bus_prog_addr] <= {2'b01, `BUSCMD_LOAD_DP };
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// bus_prog_addr <= bus_prog_addr + 5'd1;
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// addr_nibble_ptr <= 3'b0;
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// send_reg_D0_D1 <= 1'b1;
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// exec_mem_read <= 1'b1;
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// end
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// `INSTR_TYPE_MEM_WRITE:
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// begin
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// $display("CTRL %0d: [%d] MEM WRITE", i_phase, i_cycle_ctr);
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// bus_program[bus_prog_addr] <= {2'b01, `BUSCMD_LOAD_DP };
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// bus_prog_addr <= bus_prog_addr + 5'd1;
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// addr_nibble_ptr <= 3'b0;
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// send_reg_D0_D1 <= 1'b1;
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// exec_mem_write <= 1'b1;
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// end
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`INSTR_TYPE_CONFIG:
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begin
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$display("CTRL %0d: [%d] exec : CONFIG", i_phase, i_cycle_ctr);
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@ -633,15 +651,17 @@ always @(posedge i_clk) begin
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endcase
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end
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end
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/**********************************************************************************************
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*
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* sending bus programs
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*
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*********************************************************************************************/
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if (i_clk_en && control_unit_ready) begin
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/******************************************************************************************
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*
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* sending the value of the PC
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*
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*****************************************************************************************/
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if (send_reg_PC) begin
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$display("CTRL %0d: [%d] exec: send_reg_PC[%0d] %h", i_phase, i_cycle_ctr, addr_nibble_ptr, reg_PC[addr_nibble_ptr*4+:4] );
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@ -654,6 +674,12 @@ always @(posedge i_clk) begin
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end
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end
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/******************************************************************************************
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*
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* CONFIG and UNCNFG stuff
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*
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*****************************************************************************************/
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/*
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* send C(A)
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* used for CONFIG and UNCNFG
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@ -669,27 +695,11 @@ always @(posedge i_clk) begin
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end
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end
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/*
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* sends the PC_READ command to restore devices after some other bus command
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*/
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if (send_pc_read) begin
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$display("CTRL %0d: [%d] exec : RESET - send PC_READ", i_phase, i_cycle_ctr);
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_PC_READ };
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bus_prog_addr <= bus_prog_addr + 5'd1;
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send_pc_read <= 1'b0;
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end
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end
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/******************************************************************************************
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*
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* ALU pipeline
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*
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*****************************************************************************************/
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if (i_clk_en && control_unit_ready) begin
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/**********
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*
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@ -815,7 +825,113 @@ always @(posedge i_clk) begin
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if (i_phases[3] && !alu_start) begin
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$display("CTRL %0d: [%d] ALU is not started", i_phase, i_cycle_ctr);
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end
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/******************************************************************************************
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*
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* Memory operations control
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*
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*****************************************************************************************/
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// /*
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// * send D0 or D1
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// */
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// if (send_reg_D0_D1) begin
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// $display("CTRL %0d: [%d] exec: sending D%b[%0d] %h", i_phase, i_cycle_ctr,
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// dec_mem_pointer, addr_nibble_ptr,
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// dec_mem_pointer?reg_D1[addr_nibble_ptr]:reg_D0[addr_nibble_ptr]);
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// bus_program[bus_prog_addr] <= { 2'b00, dec_mem_pointer?reg_D1[addr_nibble_ptr]:reg_D0[addr_nibble_ptr]};
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// addr_nibble_ptr <= addr_nibble_ptr + 3'd1;
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// bus_prog_addr <= bus_prog_addr + 5'd1;
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// if (addr_nibble_ptr == 3'd4) begin
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// addr_nibble_ptr <= 3'd0;
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// send_reg_D0_D1 <= 1'b0;
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// send_reg_D0_D1_done <= 1'b1;
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// send_dp_write <= exec_mem_write;
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// mem_access_ptr <= dec_alu_ptr_begin;
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// end
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// end
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// /*
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// * in case of memory write, send DP_WRITE command
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// */
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// if (send_reg_D0_D1_done && send_dp_write && exec_mem_write) begin
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// $display("CTRL %0d: [%d] exec: sending DP_WRITE", i_phase, i_cycle_ctr);
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// bus_program[bus_prog_addr] <= {2'b01, `BUSCMD_DP_WRITE };
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// bus_prog_addr <= bus_prog_addr + 5'd1;
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// send_dp_write <= 1'b0;
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// end
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// /*
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// * send the data to write
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// */
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// if (send_reg_D0_D1_done && !send_dp_write && exec_mem_write) begin
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// $display("CTRL %0d: [%d] exec: writing data %c[%h] %h", i_phase, i_cycle_ctr,
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// reg_src_1_c?"C":"A", mem_access_ptr,
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// reg_src_1_c?reg_C[mem_access_ptr]:reg_A[mem_access_ptr]);
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// bus_program[bus_prog_addr] <= {2'b00, reg_src_1_c?reg_C[mem_access_ptr]:reg_A[mem_access_ptr]};
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// mem_access_ptr <= mem_access_ptr + 4'h1;
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// bus_prog_addr <= bus_prog_addr + 5'd1;
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// if (mem_access_ptr == dec_alu_ptr_end) begin
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// send_reg_D0_D1_done <= 1'b0;
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// send_pc_read <= 1'b1;
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// end
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// end
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// /*
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// * send the data to write
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// */
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// if (send_reg_D0_D1_done && exec_mem_read) begin
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// $display("CTRL %0d: [%d] exec: reading data to %c[%h]", i_phase, i_cycle_ctr,
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// reg_dest_c?"C":"A", mem_access_ptr);
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// bus_program[bus_prog_addr] <= 6'b100000;
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// mem_access_ptr <= mem_access_ptr + 4'h1;
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// bus_prog_addr <= bus_prog_addr + 5'd1;
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// if (mem_access_ptr == dec_alu_ptr_end) begin
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// send_reg_D0_D1_done <= 1'b0;
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// send_pc_read <= 1'b1;
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// mem_access_ptr <= 4'b0;
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// end
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// end
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// /*
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// * wait for something to read
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// */
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// if (exec_mem_read && i_phases[2] && i_read) begin
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// case (dec_alu_reg_dest)
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// `ALU_REG_A: reg_A[mem_access_ptr] <= i_nibble;
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// `ALU_REG_C: reg_C[mem_access_ptr] <= i_nibble;
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// default: $display("CTRL %0d: [%d] exec read: unsupported register %0d", i_phase, i_cycle_ctr, dec_alu_reg_dest);
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// endcase
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// mem_access_ptr <= mem_access_ptr + 4'h1;
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// end
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// /*
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// * wait for the program end, cleanup the exec_read and exec_write flags
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// */
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// if ((i_program_address == bus_prog_addr) &&
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// !(send_reg_D0_D1 || send_reg_D0_D1_done || send_dp_write) &&
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// (exec_mem_read || exec_mem_write)) begin
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// $display("CTRL %0d: [%d] exec: memory transfer cleanup", i_phase, i_cycle_ctr);
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// exec_mem_read <= 1'b0;
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// exec_mem_write <= 1'b0;
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// end
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/******************************************************************************************
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*
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* send the PC_READ command (many things end with this)
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*
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*****************************************************************************************/
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/*
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* sends the PC_READ command to restore devices after some other bus command
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*/
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if (send_pc_read) begin
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$display("CTRL %0d: [%d] exec : RESET - send PC_READ", i_phase, i_cycle_ctr);
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_PC_READ };
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bus_prog_addr <= bus_prog_addr + 5'd1;
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send_pc_read <= 1'b0;
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end
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end
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