mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
add mmio
fix rtn instructions decode block 14x
This commit is contained in:
Raphael Jacquot
parent
b2ae484450
commit
a1b22269b2
7 changed files with 437 additions and 29 deletions
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@ -2,6 +2,7 @@ read_verilog -I. saturn_top.v
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read_verilog -I. saturn_serial.v
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read_verilog -I. saturn_bus.v
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read_verilog -I. saturn_hp48gx_rom.v
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read_verilog -I. saturn_hp48gx_mmio.v
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read_verilog -I. saturn_bus_controller.v
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read_verilog -I. saturn_debugger.v
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read_verilog -I. saturn_control_unit.v
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2
run.sh
2
run.sh
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@ -12,7 +12,7 @@
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#iverilog -v -Wall -DSIM -o mask_gen_tb mask_gen.v
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iverilog -v -Wall -DSIM -o z_saturn_test.iv -s saturn_top \
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saturn_top.v saturn_serial.v \
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saturn_bus.v saturn_hp48gx_rom.v \
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saturn_bus.v saturn_hp48gx_rom.v saturn_hp48gx_mmio.v \
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saturn_bus_controller.v saturn_debugger.v \
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saturn_control_unit.v saturn_inst_decoder.v\
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saturn_regs_pc_rstk.v #saturn_alu_module.v
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31
saturn_bus.v
31
saturn_bus.v
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@ -82,6 +82,36 @@ saturn_hp48gx_rom hp48gx_rom (
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wire [3:0] rom_bus_nibble_out;
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/**************************************************************************************************
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*
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* this is the io-ram module
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* this module only takes one configuration parameter, size is fixed
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*
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*************************************************************************************************/
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saturn_hp48gx_mmio hp48gx_mmio (
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.i_clk (i_clk),
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.i_clk_en (i_clk_en),
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.i_reset (i_reset),
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.i_phase (phase),
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.i_phases (phases),
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.i_cycle_ctr (cycle_ctr),
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.i_debug_cycle (dbg_debug_cycle),
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.i_bus_clk_en (bus_clk_en),
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.i_bus_is_data (ctrl_bus_is_data),
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.o_bus_nibble_out (mmio_bus_nibble_out),
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.i_bus_nibble_in (ctrl_bus_nibble_out),
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.i_bus_daisy (1'b1),
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.o_bus_daisy (mmio_daisy_out),
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.o_bus_active (mmio_active)
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);
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wire [3:0] mmio_bus_nibble_out;
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wire [0:0] mmio_daisy_out;
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wire [0:0] mmio_active;
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/**************************************************************************************************
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*
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* the main processor is hidden behind this bus controller device
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@ -151,6 +181,7 @@ assign o_halt = bus_halt || ctrl_halt;
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*/
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always @(*) begin
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ctrl_bus_nibble_in = rom_bus_nibble_out;
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if (mmio_active) ctrl_bus_nibble_in = mmio_bus_nibble_out;
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end
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always @(*) begin
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@ -119,9 +119,12 @@
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`define INSTR_TYPE_SET_MODE 2
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`define INSTR_TYPE_JUMP 3
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`define INSTR_TYPE_RTN 4
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`define INSTR_TYPE_LOAD 5
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`define INSTR_TYPE_CONFIG 6
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`define INSTR_TYPE_RESET 7
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`define INSTR_TYPE_LOAD_LENGTH 5
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`define INSTR_TYPE_LOAD 6
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`define INSTR_TYPE_MEM_READ 7
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`define INSTR_TYPE_MEM_WRITE 8
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`define INSTR_TYPE_CONFIG 9
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`define INSTR_TYPE_RESET 10
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`define INSTR_TYPE_NONE 15
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345
saturn_hp48gx_mmio.v
Normal file
345
saturn_hp48gx_mmio.v
Normal file
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@ -0,0 +1,345 @@
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/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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`include "saturn_def_buscmd.v"
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module saturn_hp48gx_mmio (
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i_clk,
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i_clk_en,
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i_reset,
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i_phase,
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i_phases,
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i_cycle_ctr,
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i_debug_cycle,
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i_bus_clk_en,
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i_bus_is_data,
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o_bus_nibble_out,
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i_bus_nibble_in,
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i_bus_daisy,
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o_bus_daisy,
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o_bus_active,
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o_menu_height,
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o_rom_mode
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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input wire [1:0] i_phase;
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input wire [3:0] i_phases;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_debug_cycle;
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/**************************************************************************************************
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*
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* bus I/O
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*
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*************************************************************************************************/
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input wire [0:0] i_bus_clk_en;
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input wire [0:0] i_bus_is_data;
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output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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input wire [0:0] i_bus_daisy;
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output wire [0:0] o_bus_daisy;
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output wire [0:0] o_bus_active;
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/**************************************************************************************************
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*
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* I/O registers
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*
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*************************************************************************************************/
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output reg [5:0] o_menu_height; // 0x28 bits 0-3 | 0x29 bits 0-1
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output reg [0:0] o_rom_mode; // 0x29 bit 3
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/**************************************************************************************************
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*
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* address handling
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*
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*************************************************************************************************/
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`define MMIO_BITS 6
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reg [3:0] ioram_data[0:(2** `MMIO_BITS) - 1];
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reg [3:0] last_cmd;
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reg [2:0] addr_pos_ctr;
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reg [19:0] local_pc;
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reg [19:0] local_dp;
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reg [0:0] pc_active;
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reg [0:0] dp_active;
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reg [0:0] configured;
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reg [19:0] base_addr;
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initial begin
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last_cmd = 4'b0;
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addr_pos_ctr = 3'b0;
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local_pc = 20'b0;
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local_dp = 20'b0;
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pc_active = 1'b0;
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dp_active = 1'b0;
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configured = 1'b0;
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base_addr = 20'b0;
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end
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/*
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* testing for read
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*/
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wire [0:0] do_pc_read = (last_cmd == `BUSCMD_PC_READ);
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wire [0:0] do_dp_read = (last_cmd == `BUSCMD_DP_READ);
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wire [0:0] do_read = do_pc_read || do_dp_read;
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/*
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* testing for write
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*/
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wire [0:0] do_pc_write = (last_cmd == `BUSCMD_PC_WRITE);
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wire [0:0] do_dp_write = (last_cmd == `BUSCMD_DP_WRITE);
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wire [0:0] do_write = do_pc_write || do_dp_write;
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/*
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* accessing the ioram
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*/
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assign o_bus_daisy = configured;
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wire [0:0] use_pc = do_pc_read || do_pc_write;
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wire [0:0] use_dp = do_dp_read || do_dp_write;
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wire [19:0] above_addr = base_addr + (2 ** `MMIO_BITS);
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wire [0:0] active = ((pc_active && use_pc) || (dp_active && use_dp)) && configured;
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assign o_bus_active = active;
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wire [19:0] pointer = use_pc?local_pc:local_dp;
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wire [19:0] access_pointer = pointer - base_addr;
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wire [`MMIO_BITS-1:0] address = access_pointer[`MMIO_BITS-1:0];
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wire [0:0] gen_active = i_clk_en && !i_debug_cycle && i_phases[0] && (do_read || do_write);
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wire [0:0] can_read = i_bus_clk_en && i_clk_en && i_bus_is_data && do_read && active;
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wire [0:0] can_write = i_bus_clk_en && i_clk_en && i_bus_is_data && do_write && active;
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/*
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* reading and writing to I/O registers
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*/
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/*
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* generate the active signals
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* these comparisons incur important delays
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*/
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always @(posedge i_clk) begin
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if (gen_active) begin
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// $display("MMIO-GX %0d: [%d] use_pc %b | use_dp %b | local_pc %5h | local_dp %5h | base %5h | above %5h | conf %b", i_phase, i_cycle_ctr,
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// use_pc, use_dp, local_pc, local_dp, base_addr, above_addr, configured);
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pc_active <= use_pc && (local_pc >= base_addr) && (local_pc < above_addr) && configured;
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dp_active <= use_dp && (local_dp >= base_addr) && (local_dp < above_addr) && configured;
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end
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if (i_reset) begin
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pc_active <= 1'b0;
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dp_active <= 1'b0;
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end
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end
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always @(posedge i_clk) begin
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if (can_read)
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o_bus_nibble_out <= ioram_data[address];
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end
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reg [0:0] junk_bit_0;
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always @(posedge i_clk) begin
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if (can_write) begin
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case (address)
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6'h28: o_menu_height[3:0] <= i_bus_nibble_in;
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6'h29: {o_rom_mode, junk_bit_0, o_menu_height[5:4]} <= i_bus_nibble_in;
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default:
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begin
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`ifdef SIM
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$display("MMIO-GX %0d: [%d] addr %h not handled", i_phase, i_cycle_ctr, pointer);
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`endif
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end
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endcase
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ioram_data[address] <= i_bus_nibble_in;
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end
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end
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`ifdef SIM
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wire [3:0] imm_nibble = ioram_data[address];
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`endif
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/*
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* general case
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*/
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always @(posedge i_clk) begin
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if (i_bus_clk_en && i_clk_en) begin
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if (i_bus_is_data) begin
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/* do things with the bits...*/
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case (last_cmd)
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`BUSCMD_PC_READ:
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begin
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// o_bus_nibble_out <= rom_data[local_pc[`ROMBITS-1:0]];
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local_pc <= local_pc + 1;
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end
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`BUSCMD_DP_READ:
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begin
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// o_bus_nibble_out <= rom_data[local_dp[`ROMBITS-1:0]];
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local_dp <= local_dp + 1;
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end
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`BUSCMD_PC_WRITE: local_pc <= local_pc + 1;
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`BUSCMD_DP_WRITE: local_dp <= local_dp + 1;
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`BUSCMD_LOAD_PC:
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begin
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local_pc[addr_pos_ctr*4+:4] <= i_bus_nibble_in;
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addr_pos_ctr <= addr_pos_ctr + 3'd1;
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end
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`BUSCMD_LOAD_DP:
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begin
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local_dp[addr_pos_ctr*4+:4] <= i_bus_nibble_in;
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addr_pos_ctr <= addr_pos_ctr + 3'd1;
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end
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`BUSCMD_CONFIGURE:
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if (i_bus_daisy && !configured) begin
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base_addr[addr_pos_ctr*4+:4] <= i_bus_nibble_in;
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addr_pos_ctr <= addr_pos_ctr + 3'd1;
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end
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default: begin end
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endcase
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/* auto switch to pc read / dp read */
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if (addr_pos_ctr == 4) begin
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case (last_cmd)
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`BUSCMD_LOAD_PC: last_cmd <= `BUSCMD_PC_READ;
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`BUSCMD_LOAD_DP: last_cmd <= `BUSCMD_DP_READ;
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`BUSCMD_CONFIGURE:
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begin
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// set above_addr
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configured <= 1'b1;
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end
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default: begin end
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endcase
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end
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`ifdef SIM
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$write("MMIO-GX %0d: [%d] ", i_phase, i_cycle_ctr);
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case (last_cmd)
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`BUSCMD_PC_READ:
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begin
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$write("PC_READ ");
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if (configured)
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begin
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if (can_read) $write("<= mmio[%5h]: %h", local_pc, imm_nibble);
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else $write("inactive");
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end
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else $write("(ignore)");
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end
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`BUSCMD_DP_READ:
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begin
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$write("DP_READ ");
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if (configured)
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begin
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if (can_read) $write("<= mmio[%5h]: %h", local_dp, imm_nibble);
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else $write("(inactive)");
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end
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else $write("(ignore)");
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end
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`BUSCMD_DP_WRITE:
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begin
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$write("DP_WRITE ");
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if (configured)
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begin
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if (can_write) $write("mmio[%5h] <= %h", local_dp, i_bus_nibble_in);
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else $write("(inactive %h)", i_bus_nibble_in);
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end
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else $write("(ignore)");
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end
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`BUSCMD_LOAD_PC: $write("LOAD_PC - pc %5h, %h pos %0d", local_pc, i_bus_nibble_in, addr_pos_ctr);
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`BUSCMD_LOAD_DP: $write("LOAD_DP - dp %5h, %h pos %0d", local_dp, i_bus_nibble_in, addr_pos_ctr);
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`BUSCMD_CONFIGURE:
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begin
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if (!configured) $write("CONFIGURE - base_addr %5h, %h pos %0d", base_addr, i_bus_nibble_in, addr_pos_ctr);
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else $write("CONFIGURE - already done, ignore");
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end
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`BUSCMD_RESET: $write("RESET");
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default: $write("last_command %h nibble %h - UNHANDLED", last_cmd, i_bus_nibble_in);
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endcase
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if (addr_pos_ctr == 4) begin
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case (last_cmd)
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`BUSCMD_LOAD_PC: $write(" auto switch to PC_READ");
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`BUSCMD_LOAD_DP: $write(" auto switch to DP_READ");
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default: begin end
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endcase
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end
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$write("\n");
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`endif
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end else begin
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last_cmd <= i_bus_nibble_in;
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if ((i_bus_nibble_in == `BUSCMD_LOAD_PC) || (i_bus_nibble_in == `BUSCMD_LOAD_DP))
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addr_pos_ctr <= 0;
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if (i_bus_nibble_in == `BUSCMD_CONFIGURE)
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addr_pos_ctr <= 3'd0;
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if (i_bus_nibble_in == `BUSCMD_RESET)
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begin
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base_addr <= 20'b0;
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configured <= 1'b0;
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end
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`ifdef SIM
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$write("MMIO-GX %0d: [%d] ", i_phase, i_cycle_ctr);
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case (i_bus_nibble_in)
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`BUSCMD_PC_READ: $write("PC_READ");
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`BUSCMD_DP_READ: $write("DP_READ");
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`BUSCMD_DP_WRITE: $write("DP_WRITE");
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`BUSCMD_LOAD_PC: $write("LOAD_PC");
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`BUSCMD_LOAD_DP: $write("LOAD_DP");
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`BUSCMD_CONFIGURE: $write("CONFIGURE");
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`BUSCMD_RESET: $write("RESET base_addr to %5h and unconfigure", 20'h0);
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default: begin end
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endcase
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$write("\n");
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`endif
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end
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end
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if (i_reset) begin
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last_cmd <= 4'b0;
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addr_pos_ctr <= 3'b0;
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local_pc <= 20'b0;
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local_dp <= 20'b0;
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configured <= 1'b0;
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base_addr <= 20'b0;
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end
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end
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// Verilator lint_off UNUSED
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wire [(20 -`MMIO_BITS):0] unused;
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assign unused = { junk_bit_0, access_pointer[19:`MMIO_BITS] };
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// Verilator lint_on UNUSED
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endmodule
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@ -52,6 +52,8 @@ module saturn_inst_decoder (
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o_jump_length,
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o_block_0x,
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o_mem_pointer,
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o_instr_type,
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o_push_pc,
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o_instr_decoded,
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@ -92,6 +94,8 @@ output reg [2:0] o_jump_length;
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output wire [0:0] o_block_0x;
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assign o_block_0x = block_0x;
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output reg [0:0] o_mem_pointer;
|
||||
|
||||
output reg [3:0] o_instr_type;
|
||||
output reg [0:0] o_push_pc;
|
||||
/* instruction is fully decoded */
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||||
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|
@ -134,6 +138,7 @@ reg [0:0] decode_started;
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|||
|
||||
reg [0:0] block_0x;
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||||
reg [0:0] block_1x;
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||||
reg [0:0] block_14x;
|
||||
reg [0:0] block_2x;
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||||
reg [0:0] block_3x;
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||||
reg [0:0] block_8x;
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||||
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|
@ -186,6 +191,7 @@ initial begin
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|||
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||||
block_0x = 1'b0;
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||||
block_1x = 1'b0;
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||||
block_14x = 1'b0;
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||||
block_2x = 1'b0;
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||||
block_3x = 1'b0;
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||||
block_8x = 1'b0;
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||||
|
|
@ -319,6 +325,7 @@ always @(posedge i_clk) begin
|
|||
|
||||
if (block_1x) begin
|
||||
case (i_nibble)
|
||||
4'h4: block_14x <= 1'b1;
|
||||
4'hB:
|
||||
begin
|
||||
$display("DECODER %0d: [%d] D)=(5)", i_phase, i_cycle_ctr, i_nibble);
|
||||
|
|
@ -339,6 +346,22 @@ always @(posedge i_clk) begin
|
|||
block_1x <= 1'b0;
|
||||
end
|
||||
|
||||
if (block_14x) begin
|
||||
$display("DECODER %0d: [%d] block_14x %h", i_phase, i_cycle_ctr, i_nibble);
|
||||
o_mem_pointer <= i_nibble[0];
|
||||
o_instr_type <= i_nibble[1]?`INSTR_TYPE_MEM_READ:`INSTR_TYPE_MEM_WRITE;
|
||||
o_alu_reg_dest <= i_nibble[2]?`ALU_REG_C:`ALU_REG_A;
|
||||
o_alu_reg_src_1 <= i_nibble[2]?`ALU_REG_C:`ALU_REG_A;
|
||||
o_alu_reg_src_2 <= `ALU_REG_NONE;
|
||||
o_alu_field <= i_nibble[3]?`FT_FIELD_B:`FT_FIELD_A;
|
||||
o_alu_ptr_begin <= 4'h0;
|
||||
o_alu_ptr_end <= i_nibble[3]?1:4;
|
||||
o_instr_execute <= 1'b1;
|
||||
o_instr_decoded <= 1'b1;
|
||||
decode_started <= 1'b0;
|
||||
block_14x <= 1'b0;
|
||||
end
|
||||
|
||||
if (block_2x) begin
|
||||
o_alu_reg_dest <= `ALU_REG_P;
|
||||
o_alu_reg_src_1 <= `ALU_REG_IMM;
|
||||
|
|
@ -685,6 +708,7 @@ always @(posedge i_clk) begin
|
|||
|
||||
block_0x <= 1'b0;
|
||||
block_1x <= 1'b0;
|
||||
block_14x <= 1'b0;
|
||||
block_2x <= 1'b0;
|
||||
block_3x <= 1'b0;
|
||||
block_8x <= 1'b0;
|
||||
|
|
|
|||
|
|
@ -95,12 +95,14 @@ reg [0:0] jump_exec;
|
|||
reg [2:0] jump_counter;
|
||||
reg [19:0] jump_base;
|
||||
reg [19:0] jump_offset;
|
||||
reg [19:0] jump_rel_addr;
|
||||
|
||||
wire [0:0] jump_rel2 = i_jump_instr && (i_jump_length == 3'd1);
|
||||
wire [0:0] jump_rel3 = i_jump_instr && (i_jump_length == 3'd2);
|
||||
wire [0:0] jump_rel4 = i_jump_instr && (i_jump_length == 3'd3);
|
||||
wire [0:0] jump_abs5 = i_jump_instr && (i_jump_length == 3'd4);
|
||||
wire [0:0] jump_relative = jump_rel2 || jump_rel3 || jump_rel4;
|
||||
wire [0:0] is_rtn = i_phases[2] && i_block_0x && !i_nibble[3] && !i_nibble[2];
|
||||
|
||||
reg [19:0] jump_next_offset;
|
||||
|
||||
|
|
@ -120,6 +122,10 @@ reg [19:0] reg_PC;
|
|||
reg [2:0] reg_rstk_ptr;
|
||||
reg [19:0] reg_RSTK[0:7];
|
||||
|
||||
reg [2:0] rstk_ptr_to_push_at;
|
||||
reg [19:0] addr_to_return_to;
|
||||
reg [2:0] rstk_ptr_after_pop;
|
||||
|
||||
assign o_current_pc = reg_PC;
|
||||
|
||||
initial begin
|
||||
|
|
@ -131,6 +137,11 @@ initial begin
|
|||
jump_counter = 3'd0;
|
||||
reg_PC = 20'h00000;
|
||||
reg_rstk_ptr = 3'd7;
|
||||
|
||||
addr_to_return_to = 20'b0;
|
||||
rstk_ptr_after_pop = 3'd0;
|
||||
rstk_ptr_to_push_at = 3'd0;
|
||||
jump_rel_addr = 20'b0;
|
||||
end
|
||||
|
||||
/*
|
||||
|
|
@ -184,10 +195,13 @@ always @(posedge i_clk) begin
|
|||
* address of nibble after the offset when gosub
|
||||
*/
|
||||
if (i_phases[3] && do_jump_instr && !jump_decode) begin
|
||||
`ifdef SIM
|
||||
$display("PC_RSTK %0d: [%d] start decode jump %0d | jump_base %5h", i_phase, i_cycle_ctr, i_jump_length, reg_PC);
|
||||
`endif
|
||||
jump_counter <= 3'd0;
|
||||
jump_base <= reg_PC;
|
||||
jump_decode <= 1'b1;
|
||||
rstk_ptr_to_push_at <= (reg_rstk_ptr + 3'o1) & 3'o7;
|
||||
end
|
||||
|
||||
/* one step of the calculation (one nibble of data came in) */
|
||||
|
|
@ -209,28 +223,24 @@ always @(posedge i_clk) begin
|
|||
$write("\n");
|
||||
end
|
||||
end
|
||||
|
||||
// /* all done, apply to PC and RSTK */
|
||||
// if (i_phases[3] && do_jump_instr && jump_exec) begin
|
||||
// $write("PC_RSTK %0d: [%d] execute jump %0d", i_phase, i_cycle_ctr, i_jump_length);
|
||||
// if (i_push_pc) begin
|
||||
// $write(" ( push %5h => RSTK[%0d])", reg_PC, reg_rstk_ptr + 3'd1);
|
||||
// reg_RSTK[(reg_rstk_ptr + 3'o1)&3'o7] <= reg_PC;
|
||||
// reg_rstk_ptr <= reg_rstk_ptr + 3'd1;
|
||||
// end
|
||||
// $display("");
|
||||
// reg_PC <= jump_relative ? jump_offset + jump_base : jump_offset;
|
||||
// jump_exec <= 1'b0;
|
||||
// o_reload_pc <= 1'b0;
|
||||
// end
|
||||
end
|
||||
|
||||
/*
|
||||
* RTN instruction
|
||||
*/
|
||||
|
||||
if (i_clk_en && !i_bus_busy && !i_exec_unit_busy) begin
|
||||
/* this happens at the same time in the decoder */
|
||||
if (i_phases[2] && i_block_0x && (i_nibble[3:2] == 2'b00)) begin
|
||||
if (i_phases[1]) begin
|
||||
addr_to_return_to <= reg_RSTK[reg_rstk_ptr];
|
||||
rstk_ptr_after_pop <= (reg_rstk_ptr - 3'o1) & 3'o7;
|
||||
end
|
||||
|
||||
if (is_rtn) begin
|
||||
/* this is an RTN */
|
||||
reg_PC <= addr_to_return_to;
|
||||
reg_RSTK[reg_rstk_ptr] <= 20'h00000;
|
||||
reg_rstk_ptr <= rstk_ptr_after_pop;
|
||||
`ifdef SIM
|
||||
$write("PC_RSTK %0d: [%d] RTN", i_phase, i_cycle_ctr);
|
||||
case (i_nibble)
|
||||
4'h0: $display("SXM");
|
||||
|
|
@ -238,20 +248,14 @@ always @(posedge i_clk) begin
|
|||
4'h3: $display("CC");
|
||||
default: begin end
|
||||
endcase
|
||||
// o_reload_pc <= 1'b1;
|
||||
$display("PC_RSTK %0d: [%d] execute RTN back to %5h", i_phase, i_cycle_ctr, addr_to_return_to);
|
||||
`endif
|
||||
end
|
||||
|
||||
if (i_phases[3] && i_rtn_instr) begin
|
||||
$display("PC_RSTK %0d: [%d] execute RTN back to %5h", i_phase, i_cycle_ctr, reg_RSTK[reg_rstk_ptr]);
|
||||
reg_PC <= reg_RSTK[reg_rstk_ptr];
|
||||
reg_RSTK[reg_rstk_ptr] <= 20'h00000;
|
||||
reg_rstk_ptr <= (reg_rstk_ptr - 3'd1) & 3'd7;
|
||||
/* o_reload_pc was set in advance above */
|
||||
// o_reload_pc <= 1'b0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// if (i_phases[0] && i_clk_en) begin
|
||||
// $write("RSTK : ptr %0d | ", reg_rstk_ptr);
|
||||
// for (tmp_ctr = 4'd0; tmp_ctr < 4'd8; tmp_ctr = tmp_ctr + 4'd1)
|
||||
|
|
|
|||
Loading…
Reference in a new issue