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implement push PC to RSTK

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This commit is contained in:
Raphaël Jacquot 2019-03-04 11:52:05 +01:00
parent 908b96df6f
commit e47f12f1d7
7 changed files with 279 additions and 149 deletions
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2
saturn_bus.v
View file

@ -147,7 +147,7 @@ always @(posedge i_clk) begin
end
`ifdef SIM
if (cycle_ctr == 85) begin
if (cycle_ctr == 91) begin
bus_halt <= 1'b1;
$display("BUS %0d: [%d] enough cycles for now", phase, cycle_ctr);
end

6
saturn_bus_controller.v
View file

@ -87,6 +87,8 @@ saturn_control_unit control_unit (
.i_dbg_register (dbg_register),
.i_dbg_reg_ptr (dbg_reg_ptr),
.o_dbg_reg_nibble (ctrl_reg_nibble),
.i_dbg_rstk_ptr (dbg_rstk_ptr),
.o_dbg_rstk_val (ctrl_rstk_val),
.o_alu_reg_dest (dec_alu_reg_dest),
.o_alu_reg_src_1 (dec_alu_reg_src_1),
@ -111,6 +113,7 @@ wire [15:0] ctrl_reg_st;
wire [3:0] ctrl_reg_p;
wire [3:0] ctrl_reg_nibble;
wire [19:0] ctrl_rstk_val;
wire [4:0] dec_alu_reg_dest;
wire [4:0] dec_alu_reg_src_1;
@ -147,6 +150,8 @@ saturn_debugger debugger (
.o_dbg_register (dbg_register),
.o_dbg_reg_ptr (dbg_reg_ptr),
.i_dbg_reg_nibble (ctrl_reg_nibble),
.o_dbg_rstk_ptr (dbg_rstk_ptr),
.i_dbg_rstk_val (ctrl_rstk_val),
.i_alu_reg_dest (dec_alu_reg_dest),
.i_alu_reg_src_1 (dec_alu_reg_src_1),
@ -162,6 +167,7 @@ saturn_debugger debugger (
wire [4:0] dbg_register;
wire [3:0] dbg_reg_ptr;
wire [2:0] dbg_rstk_ptr;
wire [0:0] dbg_debug_cycle;
assign o_debug_cycle = dbg_debug_cycle;

12
saturn_control_unit.v
View file

@ -53,6 +53,8 @@ module saturn_control_unit (
i_dbg_register,
i_dbg_reg_ptr,
o_dbg_reg_nibble,
i_dbg_rstk_ptr,
o_dbg_rstk_val,
o_alu_reg_dest,
o_alu_reg_src_1,
@ -95,6 +97,8 @@ output wire [15:0] o_reg_st;
input wire [4:0] i_dbg_register;
input wire [3:0] i_dbg_reg_ptr;
output reg [3:0] o_dbg_reg_nibble;
input wire [2:0] i_dbg_rstk_ptr;
output wire [19:0] o_dbg_rstk_val;
output wire [4:0] o_alu_reg_dest;
output wire [4:0] o_alu_reg_src_1;
@ -150,6 +154,7 @@ saturn_inst_decoder instruction_decoder(
.o_jump_length (dec_jump_length),
.o_instr_type (dec_instr_type),
.o_push_pc (dec_push_pc),
.o_instr_decoded (dec_instr_decoded),
.o_instr_execute (dec_instr_execute),
@ -167,6 +172,7 @@ wire [4:0] dec_alu_opcode;
wire [2:0] dec_jump_length;
wire [3:0] dec_instr_type;
wire [0:0] dec_push_pc;
wire [0:0] dec_instr_decoded;
wire [0:0] dec_instr_execute;
@ -225,9 +231,13 @@ saturn_regs_pc_rstk regs_pc_rstk (
.i_nibble (i_nibble),
.i_jump_instr (inst_jump),
.i_jump_length (dec_jump_length),
.i_push_pc (dec_push_pc),
.o_current_pc (reg_PC),
.o_reload_pc (reload_PC)
.o_reload_pc (reload_PC),
.i_dbg_rstk_ptr (i_dbg_rstk_ptr),
.o_dbg_rstk_val (o_dbg_rstk_val)
);
/**************************************************************************************************

309
saturn_debugger.v
View file

@ -43,6 +43,8 @@ module saturn_debugger (
o_dbg_register,
o_dbg_reg_ptr,
i_dbg_reg_nibble,
o_dbg_rstk_ptr,
i_dbg_rstk_val,
i_alu_reg_dest,
i_alu_reg_src_1,
@ -77,6 +79,8 @@ output reg [4:0] o_dbg_register;
output wire [3:0] o_dbg_reg_ptr;
assign o_dbg_reg_ptr = registers_reg_ptr[3:0];
input wire [3:0] i_dbg_reg_nibble;
output reg [2:0] o_dbg_rstk_ptr;
input wire [19:0] i_dbg_rstk_val;
input wire [4:0] i_alu_reg_dest;
input wire [4:0] i_alu_reg_src_1;
@ -106,8 +110,8 @@ reg [7:0] hex[0:15];
reg [8:0] registers_ctr;
reg [7:0] registers_str[0:511];
reg [5:0] registers_state;
reg [4:0] registers_reg_ptr;
reg [6:0] registers_state;
reg [5:0] registers_reg_ptr;
reg [0:0] registers_done;
reg [0:0] carry;
@ -134,7 +138,7 @@ initial begin
hex[15] = "F";
registers_ctr = 9'd0;
registers_state = `DBG_REG_PC_STR;
registers_reg_ptr = 5'b0;
registers_reg_ptr = 6'b0;
o_dbg_register = `ALU_REG_NONE;
registers_done = 1'b0;
carry = 1'b1;
@ -166,7 +170,8 @@ always @(posedge i_clk) begin
* C: xxxxxxxxxxxxxxxx R2: xxxxxxxxxxxxxxxx RSTK3: xxxxx
* D: xxxxxxxxxxxxxxxx R3: xxxxxxxxxxxxxxxx RSTK2: xxxxx
* D0: xxxxx D1: xxxxx R4: xxxxxxxxxxxxxxxx RSTK1: xxxxx
* ADDR: xxxxx RSTK0: xxxxx
* RSTK0: xxxxx
0123456789012345678901234567890123456789012345
*
*/
if (o_debug_cycle && !debug_done) begin
@ -175,113 +180,113 @@ always @(posedge i_clk) begin
`DBG_REG_PC_STR:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "P";
5'd1: registers_str[registers_ctr] <= "C";
5'd2: registers_str[registers_ctr] <= ":";
5'd3: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "P";
6'd1: registers_str[registers_ctr] <= "C";
6'd2: registers_str[registers_ctr] <= ":";
6'd3: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd3) begin
registers_reg_ptr <= 5'd4;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd3) begin
registers_reg_ptr <= 6'd4;
registers_state <= `DBG_REG_PC_VALUE;
end
end
`DBG_REG_PC_VALUE:
begin
registers_str[registers_ctr] <= hex[i_current_pc[(registers_reg_ptr)*4+:4]];
registers_reg_ptr <= registers_reg_ptr - 1;
if (registers_reg_ptr == 5'd0) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_PC_SPACES;
end
end
`DBG_REG_PC_SPACES:
begin
registers_str[registers_ctr] <= " ";
registers_reg_ptr <= registers_reg_ptr + 1;
if (registers_reg_ptr == 5'd12) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd12) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_CARRY;
end
end
`DBG_REG_CARRY:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "C";
5'd1: registers_str[registers_ctr] <= "a";
5'd2: registers_str[registers_ctr] <= "r";
5'd3: registers_str[registers_ctr] <= "r";
5'd4: registers_str[registers_ctr] <= "y";
5'd5: registers_str[registers_ctr] <= ":";
5'd6: registers_str[registers_ctr] <= " ";
5'd7: registers_str[registers_ctr] <= hex[{3'b000,carry}];
5'd8: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "C";
6'd1: registers_str[registers_ctr] <= "a";
6'd2: registers_str[registers_ctr] <= "r";
6'd3: registers_str[registers_ctr] <= "r";
6'd4: registers_str[registers_ctr] <= "y";
6'd5: registers_str[registers_ctr] <= ":";
6'd6: registers_str[registers_ctr] <= " ";
6'd7: registers_str[registers_ctr] <= hex[{3'b000,carry}];
6'd8: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd8) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd8) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_CALC_MODE;
end
end
`DBG_REG_CALC_MODE:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "h";
5'd1: registers_str[registers_ctr] <= ":";
5'd2: registers_str[registers_ctr] <= " ";
5'd3: registers_str[registers_ctr] <= i_reg_alu_mode?"D":"H";
5'd4: registers_str[registers_ctr] <= "E";
5'd5: registers_str[registers_ctr] <= i_reg_alu_mode?"C":"X";
5'd6: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "h";
6'd1: registers_str[registers_ctr] <= ":";
6'd2: registers_str[registers_ctr] <= " ";
6'd3: registers_str[registers_ctr] <= i_reg_alu_mode?"D":"H";
6'd4: registers_str[registers_ctr] <= "E";
6'd5: registers_str[registers_ctr] <= i_reg_alu_mode?"C":"X";
6'd6: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd6) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd6) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_RSTK_PTR;
end
end
`DBG_REG_RSTK_PTR:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "r";
5'd1: registers_str[registers_ctr] <= "p";
5'd2: registers_str[registers_ctr] <= ":";
5'd3: registers_str[registers_ctr] <= " ";
5'd4: registers_str[registers_ctr] <= "?";
5'd5: registers_str[registers_ctr] <= " ";
5'd6: registers_str[registers_ctr] <= " ";
5'd7: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "r";
6'd1: registers_str[registers_ctr] <= "p";
6'd2: registers_str[registers_ctr] <= ":";
6'd3: registers_str[registers_ctr] <= " ";
6'd4: registers_str[registers_ctr] <= "?";
6'd5: registers_str[registers_ctr] <= " ";
6'd6: registers_str[registers_ctr] <= " ";
6'd7: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd7) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd7) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_RSTK7_STR;
end
end
`DBG_REG_RSTK7_STR:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "R";
5'd1: registers_str[registers_ctr] <= "S";
5'd2: registers_str[registers_ctr] <= "T";
5'd3: registers_str[registers_ctr] <= "K";
5'd4: registers_str[registers_ctr] <= "7";
5'd5: registers_str[registers_ctr] <= ":";
5'd6: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "R";
6'd1: registers_str[registers_ctr] <= "S";
6'd2: registers_str[registers_ctr] <= "T";
6'd3: registers_str[registers_ctr] <= "K";
6'd4: registers_str[registers_ctr] <= "7";
6'd5: registers_str[registers_ctr] <= ":";
6'd6: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd6) begin
registers_reg_ptr <= 5'd4;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd6) begin
registers_reg_ptr <= 6'd4;
o_dbg_rstk_ptr <= 3'd7;
registers_state <= `DBG_REG_RSTK7_VALUE;
end
end
`DBG_REG_RSTK7_VALUE:
begin
registers_str[registers_ctr] <= "?";
// registers_str[registers_ctr] <= hex[i_current_pc[(registers_reg_ptr)*4+:4]];
registers_reg_ptr <= registers_reg_ptr - 1;
if (registers_reg_ptr == 5'd0) begin
registers_reg_ptr <= 5'd0;
registers_str[registers_ctr] <= hex[i_dbg_rstk_val[(registers_reg_ptr)*4+:4]];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_NL_0;
end
end
@ -293,95 +298,95 @@ always @(posedge i_clk) begin
`DBG_REG_P:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "P";
5'd1: registers_str[registers_ctr] <= ":";
5'd2: registers_str[registers_ctr] <= " ";
5'd3: registers_str[registers_ctr] <= " ";
5'd4: registers_str[registers_ctr] <= hex[i_reg_p];
5'd5: registers_str[registers_ctr] <= " ";
5'd6: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "P";
6'd1: registers_str[registers_ctr] <= ":";
6'd2: registers_str[registers_ctr] <= " ";
6'd3: registers_str[registers_ctr] <= " ";
6'd4: registers_str[registers_ctr] <= hex[i_reg_p];
6'd5: registers_str[registers_ctr] <= " ";
6'd6: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd6) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd6) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_HST;
end
end
`DBG_REG_HST:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "H";
5'd1: registers_str[registers_ctr] <= "S";
5'd2: registers_str[registers_ctr] <= "T";
5'd3: registers_str[registers_ctr] <= ":";
5'd4: registers_str[registers_ctr] <= " ";
5'd5: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[3]}];
5'd6: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[2]}];
5'd7: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[1]}];
5'd8: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[0]}];
6'd0: registers_str[registers_ctr] <= "H";
6'd1: registers_str[registers_ctr] <= "S";
6'd2: registers_str[registers_ctr] <= "T";
6'd3: registers_str[registers_ctr] <= ":";
6'd4: registers_str[registers_ctr] <= " ";
6'd5: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[3]}];
6'd6: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[2]}];
6'd7: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[1]}];
6'd8: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[0]}];
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd8) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd8) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_HST_SPACES;
end
end
`DBG_REG_HST_SPACES:
begin
registers_str[registers_ctr] <= " ";
registers_reg_ptr <= registers_reg_ptr + 1;
if (registers_reg_ptr == 5'd5) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd5) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_ST_STR;
end
end
`DBG_REG_ST_STR:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "S";
5'd1: registers_str[registers_ctr] <= "T";
5'd2: registers_str[registers_ctr] <= ":";
5'd3: registers_str[registers_ctr] <= " ";
5'd4: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "S";
6'd1: registers_str[registers_ctr] <= "T";
6'd2: registers_str[registers_ctr] <= ":";
6'd3: registers_str[registers_ctr] <= " ";
6'd4: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd4) begin
registers_reg_ptr <= 5'd15;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd4) begin
registers_reg_ptr <= 6'd15;
registers_state <= `DBG_REG_ST_VALUE;
end
end
`DBG_REG_ST_VALUE:
begin
registers_str[registers_ctr] <= hex[{3'b000, i_reg_st[registers_reg_ptr]}];
registers_reg_ptr <= registers_reg_ptr - 1;
if (registers_reg_ptr == 5'd0) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_ST_SPACES;
end
end
`DBG_REG_ST_SPACES:
begin
registers_str[registers_ctr] <= " ";
registers_reg_ptr <= registers_reg_ptr + 1;
if (registers_reg_ptr == 5'd2) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd2) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_RSTK6_STR;
end
end
`DBG_REG_RSTK6_STR:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "R";
5'd1: registers_str[registers_ctr] <= "S";
5'd2: registers_str[registers_ctr] <= "T";
5'd3: registers_str[registers_ctr] <= "K";
5'd4: registers_str[registers_ctr] <= "6";
5'd5: registers_str[registers_ctr] <= ":";
5'd6: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "R";
6'd1: registers_str[registers_ctr] <= "S";
6'd2: registers_str[registers_ctr] <= "T";
6'd3: registers_str[registers_ctr] <= "K";
6'd4: registers_str[registers_ctr] <= "6";
6'd5: registers_str[registers_ctr] <= ":";
6'd6: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd6) begin
registers_reg_ptr <= 5'd4;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd6) begin
registers_reg_ptr <= 6'd4;
registers_state <= `DBG_REG_RSTK6_VALUE;
end
end
@ -389,9 +394,9 @@ always @(posedge i_clk) begin
begin
registers_str[registers_ctr] <= "?";
// registers_str[registers_ctr] <= hex[i_current_pc[(registers_reg_ptr)*4+:4]];
registers_reg_ptr <= registers_reg_ptr - 1;
if (registers_reg_ptr == 5'd0) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_NL_1;
end
end
@ -403,14 +408,14 @@ always @(posedge i_clk) begin
`DBG_REG_C_STR:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "C";
5'd1: registers_str[registers_ctr] <= ":";
5'd2: registers_str[registers_ctr] <= " ";
5'd3: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= "C";
6'd1: registers_str[registers_ctr] <= ":";
6'd2: registers_str[registers_ctr] <= " ";
6'd3: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd3) begin
registers_reg_ptr <= 5'd15;
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd3) begin
registers_reg_ptr <= 6'd15;
o_dbg_register <= `ALU_REG_C;
registers_state <= `DBG_REG_C_VALUE;
end
@ -418,13 +423,59 @@ always @(posedge i_clk) begin
`DBG_REG_C_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
registers_reg_ptr <= registers_reg_ptr - 1;
if (registers_reg_ptr == 5'd0) begin
registers_reg_ptr <= 5'd0;
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
o_dbg_register <= `ALU_REG_NONE;
registers_state <= `DBG_REG_END;
registers_state <= `DBG_REG_NL_6;
end
end
`DBG_REG_NL_6:
begin
registers_str[registers_ctr] <= "\n";
registers_state <= `DBG_REG_SPACES_7;
end
`DBG_REG_SPACES_7:
begin
registers_str[registers_ctr] <= " ";
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd45) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_RSTK0_STR;
end
end
`DBG_REG_RSTK0_STR:
begin
case (registers_reg_ptr)
6'd0: registers_str[registers_ctr] <= "R";
6'd1: registers_str[registers_ctr] <= "S";
6'd2: registers_str[registers_ctr] <= "T";
6'd3: registers_str[registers_ctr] <= "K";
6'd4: registers_str[registers_ctr] <= "0";
6'd5: registers_str[registers_ctr] <= ":";
6'd6: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd6) begin
registers_reg_ptr <= 6'd4;
o_dbg_rstk_ptr <= 3'd0;
registers_state <= `DBG_REG_RSTK0_VALUE;
end
end
`DBG_REG_RSTK0_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_rstk_val[(registers_reg_ptr)*4+:4]];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_NL_7;
end
end
`DBG_REG_NL_7:
begin
registers_str[registers_ctr] <= "\n";
registers_state <= `DBG_REG_END;
end
`DBG_REG_END: begin end
default: begin $display("ERROR, unknown register state %0d", registers_state); end
endcase
@ -461,7 +512,7 @@ always @(posedge i_clk) begin
counter <= 9'b0;
registers_ctr <= 9'd0;
registers_state <= `DBG_REG_PC_STR;
registers_reg_ptr <= 5'b0;
registers_reg_ptr <= 6'b0;
o_dbg_register <= `ALU_REG_NONE;
registers_done <= 1'b0;
write_out <= 1'b0;

20
saturn_def_debugger.v
View file

@ -66,5 +66,23 @@
`define DBG_REG_RSTK2_VALUE 52
`define DBG_REG_NL_5 53
`define DBG_REG_END 63
`define DBG_REG_D0_STR 54
`define DBG_REG_D0_VALUE 55
`define DBG_REG_D0_SPACES 56
`define DBG_REG_D1_STR 57
`define DBG_REG_D1_VALUE 58
`define DBG_REG_D1_SPACES 59
`define DBG_REG_R4_STR 60
`define DBG_REG_R4_VALUE 61
`define DBG_REG_R4_SPACES 62
`define DBG_REG_RSTK1_STR 63
`define DBG_REG_RSTK1_VALUE 64
`define DBG_REG_NL_6 65
`define DBG_REG_SPACES_7 66
`define DBG_REG_RSTK0_STR 67
`define DBG_REG_RSTK0_VALUE 68
`define DBG_REG_NL_7 69
`define DBG_REG_END 127
`endif

11
saturn_inst_decoder.v
View file

@ -49,6 +49,7 @@ module saturn_inst_decoder (
o_jump_length,
o_instr_type,
o_push_pc,
o_instr_decoded,
o_instr_execute,
@ -83,6 +84,7 @@ output reg [4:0] o_alu_opcode;
output reg [2:0] o_jump_length;
output reg [3:0] o_instr_type;
output reg [0:0] o_push_pc;
/* instruction is fully decoded */
output reg [0:0] o_instr_decoded;
/* instruction is sufficiently decoded to start execution */
@ -151,6 +153,7 @@ initial begin
o_alu_opcode = `ALU_OP_NOP;
o_instr_type = 4'd15;
o_push_pc = 1'd0;
o_instr_decoded = 1'b0;
o_instr_execute = 1'b0;
@ -280,7 +283,7 @@ always @(posedge i_clk) begin
case (i_nibble)
4'h0: block_80x <= 1'b1;
4'h2: block_82x <= 1'b1;
4'h4, 4'h5:
4'h4, 4'h5:
begin
o_alu_reg_dest <= `ALU_REG_ST;
o_alu_reg_src_1 <= `ALU_REG_IMM;
@ -290,10 +293,10 @@ always @(posedge i_clk) begin
o_instr_type <= `INSTR_TYPE_ALU;
block_84x_85x <= 1'b1;
end
4'hD, 4'hF:
4'hD, 4'hF: /* GOVLNG or GOSBVL */
begin
o_instr_type <= `INSTR_TYPE_JUMP;
o_push_pc <= 1'b1;
o_push_pc <= i_nibble[1];
o_jump_length <= 3'd4;
jump_counter <= 3'd0;
o_instr_execute <= 1'b1;
@ -394,6 +397,7 @@ always @(posedge i_clk) begin
o_instr_decoded <= 1'b0;
o_instr_execute <= 1'b0;
o_instr_type <= `INSTR_TYPE_NONE;
o_push_pc <= 1'b0;
end
end
@ -410,6 +414,7 @@ always @(posedge i_clk) begin
o_alu_opcode <= `ALU_OP_NOP;
o_instr_type <= 4'd15;
o_push_pc <= 1'b0;
o_instr_decoded <= 1'b0;
o_instr_execute <= 1'b0;

68
saturn_regs_pc_rstk.v
View file

@ -33,9 +33,14 @@ module saturn_regs_pc_rstk (
i_nibble,
i_jump_instr,
i_jump_length,
i_push_pc,
o_current_pc,
o_reload_pc
o_reload_pc,
/* debugger access */
i_dbg_rstk_ptr,
o_dbg_rstk_val
);
input wire [0:0] i_clk;
@ -50,10 +55,16 @@ input wire [0:0] i_bus_busy;
input wire [3:0] i_nibble;
input wire [0:0] i_jump_instr;
input wire [2:0] i_jump_length;
input wire [0:0] i_push_pc;
output wire [19:0] o_current_pc;
output reg [0:0] o_reload_pc;
input wire [2:0] i_dbg_rstk_ptr;
output wire [19:0] o_dbg_rstk_val;
assign o_dbg_rstk_val = reg_RSTK[i_dbg_rstk_ptr];
/**************************************************************************************************
*
* pc and rstk handling module
@ -67,6 +78,7 @@ wire [0:0] do_jump_instr = !just_reset && i_jump_instr;
*/
reg [0:0] just_reset;
reg [2:0] init_counter;
reg [0:0] jump_decode;
reg [0:0] jump_exec;
reg [2:0] jump_counter;
@ -93,17 +105,21 @@ always @(*) begin
end
reg [19:0] PC;
reg [19:0] reg_PC;
reg [2:0] reg_rstk_ptr;
reg [19:0] reg_RSTK[0:7];
assign o_current_pc = PC;
assign o_current_pc = reg_PC;
initial begin
o_reload_pc = 1'b0;
just_reset = 1'b1;
init_counter = 3'd0;
jump_decode = 1'b0;
jump_exec = 1'b0;
jump_counter = 3'd0;
PC = 20'h00000;
reg_PC = 20'h00000;
reg_rstk_ptr = 3'd7;
end
/*
@ -111,7 +127,14 @@ end
*/
always @(posedge i_clk) begin
/* initialize RSTK */
if (just_reset || (init_counter != 0)) begin
$display("PC_RSTK %0d: [%d] initializing RSTK[%0d]", i_phase, i_cycle_ctr, init_counter);
reg_RSTK[init_counter] <= 20'h00000;
init_counter <= init_counter + 3'd1;
end
/*
* only do something when nothing is busy doing some other tasks
* either talking to the bus, or debugging something
@ -128,8 +151,8 @@ always @(posedge i_clk) begin
end
if (i_phases[1] && !just_reset) begin
$display("PC_RSTK %0d: [%d] inc_pc %5h => %5h", i_phase, i_cycle_ctr, PC, PC + 20'h00001);
PC <= PC + 20'h00001;
$display("PC_RSTK %0d: [%d] inc_pc %5h => %5h", i_phase, i_cycle_ctr, reg_PC, reg_PC + 20'h00001);
reg_PC <= reg_PC + 20'h00001;
end
/*
@ -138,9 +161,9 @@ always @(posedge i_clk) begin
/* start the jump instruction */
if (i_phases[3] && do_jump_instr && !jump_decode && !jump_exec) begin
$display("PC_RSTK %0d: [%d] start decode jump %0d | jump_base %5h", i_phase, i_cycle_ctr, i_jump_length, PC);
$display("PC_RSTK %0d: [%d] start decode jump %0d | jump_base %5h", i_phase, i_cycle_ctr, i_jump_length, reg_PC);
jump_counter <= 3'd0;
jump_base <= PC;
jump_base <= reg_PC;
jump_decode <= 1'b1;
end
@ -156,24 +179,41 @@ always @(posedge i_clk) begin
end
end
/* all done, apply to PC */
/* all done, apply to PC and RSTK */
if (i_phases[3] && do_jump_instr && jump_exec) begin
$display("PC_RSTK %0d: [%d] execute jump %0d ", i_phase, i_cycle_ctr, i_jump_length);
PC <= jump_relative ? jump_offset + jump_base : jump_offset;
$write("PC_RSTK %0d: [%d] execute jump %0d", i_phase, i_cycle_ctr, i_jump_length);
if (i_push_pc) begin
$write(" ( push %5h => RSTK[%0d])", reg_PC, reg_rstk_ptr + 3'd1);
reg_RSTK[reg_rstk_ptr + 3'd1] <= reg_PC;
reg_rstk_ptr <= reg_rstk_ptr + 3'd1;
end
$display("");
reg_PC <= jump_relative ? jump_offset + jump_base : jump_offset;
jump_exec <= 1'b0;
o_reload_pc <= 1'b0;
end
end
if (i_phases[0] && i_clk_en) begin
$write("RSTK : ptr %0d | ", reg_rstk_ptr);
for (tmp_ctr = 4'd0; tmp_ctr < 4'd8; tmp_ctr = tmp_ctr + 4'd1)
$write("%0d => %5h | ", tmp_ctr, reg_RSTK[tmp_ctr]);
$write("\n");
end
if (i_reset) begin
o_reload_pc <= 1'b0;
just_reset <= 1'b1;
init_counter <= 3'd0;
jump_decode <= 1'b0;
jump_exec <= 1'b0;
jump_counter <= 3'd0;
PC <= 20'h00000;
reg_PC <= 20'h00000;
reg_rstk_ptr <= 3'd7;
end
end
reg [3:0] tmp_ctr;
endmodule