mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-24 21:59:33 +01:00
cleanup the startup procedure
This commit is contained in:
Raphael Jacquot
parent
9c05be1152
commit
a533e4ea37
4 changed files with 50 additions and 66 deletions
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@ -162,7 +162,7 @@ saturn_debugger debugger (
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.i_cycle_ctr (i_cycle_ctr),
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.o_debug_cycle (dbg_debug_cycle),
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.i_alu_busy (alu_busy),
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// .i_alu_busy (alu_busy),
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.i_exec_unit_busy (exec_unit_busy),
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/* debugger interface */
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@ -240,7 +240,7 @@ wire [0:0] inst_alu_other = inst_alu &&
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);
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wire [0:0] alu_busy = inst_alu_other || alu_start;
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wire [0:0] jump_busy = (inst_jump && dec_instr_decoded) || send_reg_PC;
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wire [0:0] jump_busy = (inst_jump && dec_instr_decoded) || send_reg_PC || just_reset;
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wire [0:0] rtn_busy = (inst_rtn && dec_instr_decoded) || send_reg_PC;
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wire [0:0] reset_busy = inst_reset;
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wire [0:0] config_busy = inst_config;
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@ -260,7 +260,7 @@ saturn_regs_pc_rstk regs_pc_rstk (
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.i_cycle_ctr (i_cycle_ctr),
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.i_bus_busy (i_bus_busy),
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.i_alu_busy (o_alu_busy),
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// .i_alu_busy (o_alu_busy),
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.i_exec_unit_busy (o_exec_unit_busy),
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.i_nibble (i_nibble),
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@ -293,6 +293,11 @@ reg [3:0] reg_C[0:15];
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reg [3:0] reg_D[0:15];
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reg [3:0] reg_D0[0:4];
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reg [3:0] reg_D1[0:4];
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reg [3:0] reg_R0[0:15];
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reg [3:0] reg_R1[0:15];
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reg [3:0] reg_R2[0:15];
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reg [3:0] reg_R3[0:15];
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reg [3:0] reg_R4[0:15];
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reg [3:0] reg_HST;
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reg [15:0] reg_ST;
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reg [3:0] reg_P;
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@ -379,6 +384,11 @@ always @(i_dbg_register, i_dbg_reg_ptr) begin
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`ALU_REG_D: o_dbg_reg_nibble = reg_D[i_dbg_reg_ptr];
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`ALU_REG_D0: o_dbg_reg_nibble = reg_D0[i_dbg_reg_ptr[2:0]];
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`ALU_REG_D1: o_dbg_reg_nibble = reg_D1[i_dbg_reg_ptr[2:0]];
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`ALU_REG_R0: o_dbg_reg_nibble = reg_R0[i_dbg_reg_ptr];
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`ALU_REG_R1: o_dbg_reg_nibble = reg_R1[i_dbg_reg_ptr];
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`ALU_REG_R2: o_dbg_reg_nibble = reg_R2[i_dbg_reg_ptr];
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`ALU_REG_R3: o_dbg_reg_nibble = reg_R3[i_dbg_reg_ptr];
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`ALU_REG_R4: o_dbg_reg_nibble = reg_R4[i_dbg_reg_ptr];
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default: o_dbg_reg_nibble = 4'h0;
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endcase
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end
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@ -438,62 +448,34 @@ always @(posedge i_clk) begin
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if (just_reset || (init_counter != 0)) begin
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$display("CTRL %0d: [%d] initializing registers %0d", i_phase, i_cycle_ctr, init_counter);
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reg_A[init_counter] <= 4'h0;
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reg_B[init_counter] <= 4'h0;
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reg_C[init_counter] <= 4'h0;
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reg_D[init_counter] <= 4'h0;
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reg_A[init_counter] <= 4'h0;
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reg_B[init_counter] <= 4'h0;
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reg_C[init_counter] <= 4'h0;
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reg_D[init_counter] <= 4'h0;
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reg_D0[init_counter] <= 4'h0;
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reg_D1[init_counter] <= 4'h0;
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reg_R0[init_counter] <= 4'h0;
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reg_R1[init_counter] <= 4'h0;
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reg_R2[init_counter] <= 4'h0;
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reg_R3[init_counter] <= 4'h0;
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reg_R4[init_counter] <= 4'h0;
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init_counter <= init_counter + 4'b1;
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end
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/************************
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*
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* we're just starting, load the PC into the controller and modules
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* this could also be used when loading the PC on jumps, need to identify conditions
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*
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*/
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if (i_clk_en && just_reset && i_phases[3]) begin
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/* this happend right after reset */
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`ifdef SIM
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$display("CTRL %0d: [%d] we were just reset, loading PC", i_phase, i_cycle_ctr);
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`endif
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just_reset <= 1'b0;
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/* this loads the PC to the modules */
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_LOAD_PC };
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`ifdef SIM
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$display("CTRL %0d: [%d] pushing LOAD_PC command to pos %d", i_phase, i_cycle_ctr, bus_prog_addr);
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`endif
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addr_nibble_ptr <= 3'b0;
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bus_prog_addr <= bus_prog_addr + 5'd1;
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load_pc_loop <= 1'b1;
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end
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/* loop to fill the initial PC value in the program */
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if (i_clk_en && load_pc_loop) begin
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/*
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* this should load the actual PC values...
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*/
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bus_program[bus_prog_addr] <= {1'b0, reg_PC_nibble };
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addr_nibble_ptr <= addr_nibble_ptr + 3'd1;
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bus_prog_addr <= bus_prog_addr + 5'd1;
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`ifdef SIM
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if (addr_nibble_ptr == 3'd0)
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$display("CTRL %0d: [%d] new PC value %5h", i_phase, i_cycle_ctr, reg_PC);
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$write("CTRL %0d: [%d] pushing ADDR : prog[%2d] <= PC[%0d] (%h)", i_phase, i_cycle_ctr,
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bus_prog_addr, addr_nibble_ptr, {1'b0, reg_PC_nibble });
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`endif
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if (addr_nibble_ptr == 3'd4) begin
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load_pc_loop <= 1'b0;
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/************************
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*
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* all registers are initialized.
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* load the PC into the controller and modules
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*
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*/
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if (init_counter == 4'hF) begin
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just_reset <= 1'b0;
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$display("CTRL %0d: [%d] pushing LOAD_PC command to pos %d", i_phase, i_cycle_ctr, bus_prog_addr);
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_LOAD_PC };
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bus_prog_addr <= bus_prog_addr + 5'd1;
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addr_nibble_ptr <= 3'b0;
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send_reg_PC <= 1'b1;
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control_unit_ready <= 1'b1;
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`ifdef SIM
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$write(" done");
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`endif
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end
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`ifdef SIM
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$write("\n");
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`endif
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end
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/************************
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@ -503,14 +485,6 @@ always @(posedge i_clk) begin
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*/
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if (i_clk_en && control_unit_ready && !i_bus_busy) begin
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// `ifdef SIM
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// $display("CTRL %0d: [%d] starting to do things", i_phase, i_cycle_ctr);
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// `endif
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// if (i_phases[2]) begin
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// $display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
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// end
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if (i_phases[3] && dec_instr_execute) begin
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case (dec_instr_type)
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@ -190,7 +190,9 @@ end
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always @(posedge i_clk) begin
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if (i_clk_en && i_phases[3] && i_instr_decoded && !debug_done && !i_exec_unit_busy) begin
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$display("DEBUGGER %0d: [%d] start debugger cycle (alu_busy %b)", i_phase, i_cycle_ctr, i_alu_busy);
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`ifdef SIM
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$display("DEBUGGER %0d: [%d] start debugger cycle (exec_unit_busy %b)", i_phase, i_cycle_ctr, i_exec_unit_busy);
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`endif
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o_debug_cycle <= 1'b1;
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registers_ctr <= 9'd0;
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registers_state <= `DBG_REG_PC_STR;
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@ -141,9 +141,17 @@ always @(posedge i_clk) begin
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/* initialize RSTK */
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if (just_reset || (init_counter != 0)) begin
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`ifdef SIM
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$display("PC_RSTK %0d: [%d] initializing RSTK[%0d]", i_phase, i_cycle_ctr, init_counter);
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`endif
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reg_RSTK[init_counter] <= 20'h00000;
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init_counter <= init_counter + 3'd1;
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if (init_counter == 3'd7) begin
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`ifdef SIM
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$display("PC_RSTK %0d: [%d] exit from reset mode", i_phase, i_cycle_ctr);
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`endif
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just_reset <= 1'b0;
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end
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end
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/*
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@ -156,10 +164,10 @@ always @(posedge i_clk) begin
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if (i_clk_en && !i_bus_busy && !i_exec_unit_busy) begin
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if (i_phases[3] && just_reset) begin
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$display("PC_RSTK %0d: [%d] exit from reset mode", i_phase, i_cycle_ctr);
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just_reset <= 1'b0;
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end
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// if (i_phases[3] && just_reset) begin
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// $display("PC_RSTK %0d: [%d] exit from reset mode", i_phase, i_cycle_ctr);
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// just_reset <= 1'b0;
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// end
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if (i_phases[1] && !just_reset) begin
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$display("PC_RSTK %0d: [%d] inc_pc %5h => %5h", i_phase, i_cycle_ctr, reg_PC, reg_PC + 20'h00001);
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