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https://github.com/sxpert/hp-saturn
synced 2024-09-28 15:20:27 +02:00
connect debugger to leds
This commit is contained in:
parent
a6d5491619
commit
b58be38b10
5 changed files with 52 additions and 26 deletions
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@ -23,12 +23,14 @@
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module saturn_bus (
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i_clk,
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i_reset,
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o_halt
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o_halt,
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o_char_to_send
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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output wire [0:0] o_halt;
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output wire [7:0] o_char_to_send;
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/**************************************************************************************************
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*
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@ -73,6 +75,7 @@ saturn_bus_controller bus_controller (
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// more ports should show up to allow for output to the serial port of debug information
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.o_debug_cycle (dbg_debug_cycle),
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.o_char_to_send (o_char_to_send),
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.o_halt (ctrl_halt)
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);
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@ -33,6 +33,7 @@ module saturn_bus_controller (
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i_bus_nibble_in,
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o_debug_cycle,
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o_char_to_send,
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o_halt
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);
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@ -48,6 +49,7 @@ output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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output wire [0:0] o_debug_cycle;
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output wire [7:0] o_char_to_send;
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output wire [0:0] o_halt;
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/**************************************************************************************************
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@ -128,7 +130,9 @@ saturn_debugger debugger (
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.i_alu_opcode (dec_alu_opcode),
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.i_instr_type (dec_instr_type),
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.i_instr_decoded (dec_instr_decoded)
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.i_instr_decoded (dec_instr_decoded),
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.o_char_to_send (o_char_to_send)
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);
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wire [0:0] dbg_debug_cycle;
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@ -283,9 +283,9 @@ always @(posedge i_clk) begin
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$display("CTRL %0d: [%d] enough cycles for now", i_phase, i_cycle_ctr);
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end
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if (i_phases[2]) begin
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$display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
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end
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// if (i_phases[2]) begin
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// $display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
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// end
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if (i_phases[3] && dec_instr_execute) begin
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case (dec_instr_type)
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@ -41,7 +41,10 @@ module saturn_debugger (
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i_alu_opcode,
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i_instr_type,
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i_instr_decoded
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i_instr_decoded,
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/* output to leds */
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o_char_to_send
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);
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input wire [0:0] i_clk;
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@ -64,13 +67,17 @@ input wire [4:0] i_alu_opcode;
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input wire [3:0] i_instr_type;
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input wire [0:0] i_instr_decoded;
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output reg [7:0] o_char_to_send;
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/**************************************************************************************************
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*
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* debugger process registers
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*
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*************************************************************************************************/
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reg [9:0] counter;
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reg [8:0] counter;
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reg [0:0] write_out;
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wire [0:0] debug_done;
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assign debug_done = registers_done;
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@ -87,7 +94,8 @@ reg [0:0] carry;
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initial begin
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o_debug_cycle = 1'b0;
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counter = 4'b0;
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counter = 9'd0;
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write_out = 1'b0;
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hex[0] = "0";
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hex[1] = "1";
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hex[2] = "2";
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@ -104,7 +112,7 @@ initial begin
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hex[13] = "D";
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hex[14] = "E";
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hex[15] = "F";
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registers_ctr = 10'd0;
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registers_ctr = 9'd0;
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registers_state = `DBG_REG_PC_STR;
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registers_reg_ptr = 5'b0;
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registers_done = 1'b0;
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@ -122,7 +130,8 @@ always @(posedge i_clk) begin
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if (i_phases[3] && i_instr_decoded) begin
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$display("DEBUGGER %0d: [%d] start debugger cycle", i_phase, i_cycle_ctr);
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o_debug_cycle <= 1'b1;
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registers_ctr <= 10'b0;
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counter <= 9'd0;
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registers_ctr <= 9'd0;
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registers_state <= `DBG_REG_PC_STR;
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end
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@ -203,26 +212,36 @@ always @(posedge i_clk) begin
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registers_ctr <= registers_ctr + 9'd1;
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end
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if (o_debug_cycle && debug_done) begin
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if (o_debug_cycle && debug_done && !write_out) begin
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$display("DEBUGGER %0d: [%d] end debugger cycle", i_phase, i_cycle_ctr);
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write_out <= 1'b1;
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end
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if (write_out) begin
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o_char_to_send <= registers_str[counter];
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counter <= counter + 9'd1;
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`ifdef SIM
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$display("%0d chars", registers_ctr);
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for (counter = 0; counter != registers_ctr; counter = counter + 1)
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$write("%c", registers_str[counter]);
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$write("$");
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$display("");
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$write("%c", registers_str[counter]);
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`endif
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registers_done <= 1'b0;
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o_debug_cycle <= 1'b0;
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if (counter == registers_ctr) begin
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`ifdef SIM
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$write("$ %0d chars written", counter + 9'd1);
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$display("");
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`endif
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write_out <= 1'b0;
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registers_done <= 1'b0;
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o_debug_cycle <= 1'b0;
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end
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end
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if (i_reset) begin
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o_debug_cycle <= 1'b0;
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counter <= 4'b0;
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registers_ctr <= 10'd0;
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counter <= 9'b0;
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registers_ctr <= 9'd0;
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registers_state <= `DBG_REG_PC_STR;
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registers_reg_ptr <= 5'b0;
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registers_done <= 1'b0;
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write_out <= 1'b0;
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end
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end
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12
saturn_top.v
12
saturn_top.v
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@ -31,17 +31,16 @@ module saturn_top (
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input wire [0:0] clk_25mhz;
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input wire [6:0] btn;
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output reg [7:0] led;
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`endif
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`ifdef SIM
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wire [0:0] clk;
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`endif
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wire [7:0] led;
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`else
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output wire [7:0] led;
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wire [0:0] reset;
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wire [0:0] halt;
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assign reset = btn[0];
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assign led[0] = halt;
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`endif
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saturn_bus main_bus (
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@ -51,7 +50,8 @@ saturn_bus main_bus (
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.i_clk (clk_25mhz),
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`endif
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.i_reset (reset),
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.o_halt (halt)
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.o_halt (halt),
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.o_char_to_send (led)
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);
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