connect debugger to leds

This commit is contained in:
Raphaël Jacquot 2019-03-03 13:33:32 +01:00
parent a6d5491619
commit b58be38b10
5 changed files with 52 additions and 26 deletions

View file

@ -23,12 +23,14 @@
module saturn_bus (
i_clk,
i_reset,
o_halt
o_halt,
o_char_to_send
);
input wire [0:0] i_clk;
input wire [0:0] i_reset;
output wire [0:0] o_halt;
output wire [7:0] o_char_to_send;
/**************************************************************************************************
*
@ -73,6 +75,7 @@ saturn_bus_controller bus_controller (
// more ports should show up to allow for output to the serial port of debug information
.o_debug_cycle (dbg_debug_cycle),
.o_char_to_send (o_char_to_send),
.o_halt (ctrl_halt)
);

View file

@ -33,6 +33,7 @@ module saturn_bus_controller (
i_bus_nibble_in,
o_debug_cycle,
o_char_to_send,
o_halt
);
@ -48,6 +49,7 @@ output reg [3:0] o_bus_nibble_out;
input wire [3:0] i_bus_nibble_in;
output wire [0:0] o_debug_cycle;
output wire [7:0] o_char_to_send;
output wire [0:0] o_halt;
/**************************************************************************************************
@ -128,7 +130,9 @@ saturn_debugger debugger (
.i_alu_opcode (dec_alu_opcode),
.i_instr_type (dec_instr_type),
.i_instr_decoded (dec_instr_decoded)
.i_instr_decoded (dec_instr_decoded),
.o_char_to_send (o_char_to_send)
);
wire [0:0] dbg_debug_cycle;

View file

@ -283,9 +283,9 @@ always @(posedge i_clk) begin
$display("CTRL %0d: [%d] enough cycles for now", i_phase, i_cycle_ctr);
end
if (i_phases[2]) begin
$display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
end
// if (i_phases[2]) begin
// $display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
// end
if (i_phases[3] && dec_instr_execute) begin
case (dec_instr_type)

View file

@ -41,7 +41,10 @@ module saturn_debugger (
i_alu_opcode,
i_instr_type,
i_instr_decoded
i_instr_decoded,
/* output to leds */
o_char_to_send
);
input wire [0:0] i_clk;
@ -64,13 +67,17 @@ input wire [4:0] i_alu_opcode;
input wire [3:0] i_instr_type;
input wire [0:0] i_instr_decoded;
output reg [7:0] o_char_to_send;
/**************************************************************************************************
*
* debugger process registers
*
*************************************************************************************************/
reg [9:0] counter;
reg [8:0] counter;
reg [0:0] write_out;
wire [0:0] debug_done;
assign debug_done = registers_done;
@ -87,7 +94,8 @@ reg [0:0] carry;
initial begin
o_debug_cycle = 1'b0;
counter = 4'b0;
counter = 9'd0;
write_out = 1'b0;
hex[0] = "0";
hex[1] = "1";
hex[2] = "2";
@ -104,7 +112,7 @@ initial begin
hex[13] = "D";
hex[14] = "E";
hex[15] = "F";
registers_ctr = 10'd0;
registers_ctr = 9'd0;
registers_state = `DBG_REG_PC_STR;
registers_reg_ptr = 5'b0;
registers_done = 1'b0;
@ -122,7 +130,8 @@ always @(posedge i_clk) begin
if (i_phases[3] && i_instr_decoded) begin
$display("DEBUGGER %0d: [%d] start debugger cycle", i_phase, i_cycle_ctr);
o_debug_cycle <= 1'b1;
registers_ctr <= 10'b0;
counter <= 9'd0;
registers_ctr <= 9'd0;
registers_state <= `DBG_REG_PC_STR;
end
@ -203,26 +212,36 @@ always @(posedge i_clk) begin
registers_ctr <= registers_ctr + 9'd1;
end
if (o_debug_cycle && debug_done) begin
if (o_debug_cycle && debug_done && !write_out) begin
$display("DEBUGGER %0d: [%d] end debugger cycle", i_phase, i_cycle_ctr);
write_out <= 1'b1;
end
if (write_out) begin
o_char_to_send <= registers_str[counter];
counter <= counter + 9'd1;
`ifdef SIM
$display("%0d chars", registers_ctr);
for (counter = 0; counter != registers_ctr; counter = counter + 1)
$write("%c", registers_str[counter]);
$write("$");
$display("");
$write("%c", registers_str[counter]);
`endif
registers_done <= 1'b0;
o_debug_cycle <= 1'b0;
if (counter == registers_ctr) begin
`ifdef SIM
$write("$ %0d chars written", counter + 9'd1);
$display("");
`endif
write_out <= 1'b0;
registers_done <= 1'b0;
o_debug_cycle <= 1'b0;
end
end
if (i_reset) begin
o_debug_cycle <= 1'b0;
counter <= 4'b0;
registers_ctr <= 10'd0;
counter <= 9'b0;
registers_ctr <= 9'd0;
registers_state <= `DBG_REG_PC_STR;
registers_reg_ptr <= 5'b0;
registers_done <= 1'b0;
write_out <= 1'b0;
end
end

View file

@ -31,17 +31,16 @@ module saturn_top (
input wire [0:0] clk_25mhz;
input wire [6:0] btn;
output reg [7:0] led;
`endif
`ifdef SIM
wire [0:0] clk;
`endif
wire [7:0] led;
`else
output wire [7:0] led;
wire [0:0] reset;
wire [0:0] halt;
assign reset = btn[0];
assign led[0] = halt;
`endif
saturn_bus main_bus (
@ -51,7 +50,8 @@ saturn_bus main_bus (
.i_clk (clk_25mhz),
`endif
.i_reset (reset),
.o_halt (halt)
.o_halt (halt),
.o_char_to_send (led)
);