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add a counter to slow things down

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This commit is contained in:
Raphaël Jacquot 2019-03-03 15:19:07 +01:00
parent ca29b542c3
commit 6dd38500a8
8 changed files with 97 additions and 41 deletions
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20
saturn_bus.v
View file

@ -22,12 +22,14 @@
module saturn_bus (
i_clk,
i_clk_en,
i_reset,
o_halt,
o_char_to_send
);
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
output wire [0:0] o_halt;
output wire [7:0] o_char_to_send;
@ -41,11 +43,12 @@ output wire [7:0] o_char_to_send;
saturn_hp48gx_rom hp48gx_rom (
.i_clk (i_clk),
.i_clk_en (i_clk_en),
.i_reset (i_reset),
.i_phase (phase),
.i_cycle_ctr (cycle_ctr),
.i_bus_clk_en (ctrl_bus_clk_en),
.i_bus_clk_en (bus_clk_en),
.i_bus_is_data (ctrl_bus_is_data),
.o_bus_nibble_out (rom_bus_nibble_out),
.i_bus_nibble_in (ctrl_bus_nibble_out)
@ -62,6 +65,7 @@ wire [3:0] rom_bus_nibble_out;
saturn_bus_controller bus_controller (
.i_clk (i_clk),
.i_clk_en (i_clk_en),
.i_reset (i_reset),
.i_phases (phases),
.i_phase (phase),
@ -94,10 +98,12 @@ wire [0:0] ctrl_halt;
*
*************************************************************************************************/
reg [0:0] bus_halt;
reg [3:0] phases;
reg [1:0] phase;
reg [31:0] cycle_ctr;
reg [0:0] bus_halt;
reg [3:0] phases;
reg [1:0] phase;
reg [31:0] cycle_ctr;
wire [0:0] bus_clk_en = i_clk_en && ctrl_bus_clk_en;
initial begin
bus_halt = 1'b0;
@ -125,13 +131,13 @@ end
always @(posedge i_clk) begin
/* if we're not debugging, advance phase on each clock */
if (!dbg_debug_cycle) begin
if (!dbg_debug_cycle && i_clk_en) begin
phases <= {phases[2:0], phases[3]};
/* using phases[3] here becase it will be phase_0 on the next step,
* so we get to a new cycle on the first phase...
*/
cycle_ctr <= cycle_ctr + {31'b0, phases[3]};
end
end
if (i_reset) begin
phases <= 4'b1;

12
saturn_bus_controller.v
View file

@ -22,6 +22,7 @@
module saturn_bus_controller (
i_clk,
i_clk_en,
i_reset,
i_phases,
i_phase,
@ -38,6 +39,7 @@ module saturn_bus_controller (
);
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
input wire [3:0] i_phases;
input wire [1:0] i_phase;
@ -60,11 +62,11 @@ output wire [0:0] o_halt;
saturn_control_unit control_unit (
.i_clk (i_clk),
.i_clk_en (bus_clk_en),
.i_reset (i_reset),
.i_phases (i_phases),
.i_phase (i_phase),
.i_cycle_ctr (i_cycle_ctr),
.i_debug_cycle (dbg_debug_cycle),
.i_bus_busy (bus_busy),
.o_program_address (ctrl_unit_prog_addr),
.i_program_address (bus_prog_addr),
@ -113,6 +115,7 @@ wire [0:0] dec_instr_decoded;
saturn_debugger debugger (
.i_clk (i_clk),
.i_clk_en (i_clk_en),
.i_reset (i_reset),
.i_phases (i_phases),
.i_phase (i_phase),
@ -148,8 +151,9 @@ assign o_debug_cycle = dbg_debug_cycle;
* local registers
*/
reg [0:0] bus_error;
reg [0:0] bus_busy;
reg [0:0] bus_error;
reg [0:0] bus_busy;
wire [0:0] bus_clk_en = !o_debug_cycle && i_clk_en;
/*
* program list for the bus controller
@ -181,7 +185,7 @@ end
*/
always @(posedge i_clk) begin
if (!o_debug_cycle) begin
if (bus_clk_en) begin
case (i_phases)
4'b0001:
begin

26
saturn_control_unit.v
View file

@ -25,11 +25,11 @@
module saturn_control_unit (
i_clk,
i_clk_en,
i_reset,
i_phases,
i_phase,
i_cycle_ctr,
i_debug_cycle,
i_bus_busy,
@ -57,11 +57,11 @@ module saturn_control_unit (
);
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
input wire [3:0] i_phases;
input wire [1:0] i_phase;
input wire [31:0] i_cycle_ctr;
input wire [0:0] i_debug_cycle;
input wire [0:0] i_bus_busy;
@ -107,11 +107,11 @@ assign o_instr_decoded = dec_instr_decoded;
saturn_inst_decoder instruction_decoder(
.i_clk (i_clk),
.i_clk_en (i_clk_en),
.i_reset (i_reset),
.i_phases (i_phases),
.i_phase (i_phase),
.i_cycle_ctr (i_cycle_ctr),
.i_debug_cycle (i_debug_cycle),
.i_bus_busy (i_bus_busy),
@ -165,11 +165,11 @@ wire [0:0] inst_alu_other = !(inst_alu_p_eq_n);
saturn_regs_pc_rstk regs_pc_rstk (
.i_clk (i_clk),
.i_clk_en (i_clk_en),
.i_reset (i_reset),
.i_phases (i_phases),
.i_phase (i_phase),
.i_cycle_ctr (i_cycle_ctr),
.i_debug_cycle (i_debug_cycle),
.i_bus_busy (i_bus_busy),
@ -193,12 +193,12 @@ wire [19:0] reg_PC;
*
*************************************************************************************************/
reg [0:0] control_unit_error;
reg [0:0] just_reset;
reg [0:0] control_unit_ready;
reg [4:0] bus_program[0:31];
reg [4:0] bus_prog_addr;
reg [2:0] addr_nibble_ptr;
reg [0:0] control_unit_error;
reg [0:0] just_reset;
reg [0:0] control_unit_ready;
reg [4:0] bus_program[0:31];
reg [4:0] bus_prog_addr;
reg [2:0] addr_nibble_ptr;
wire [3:0] reg_PC_nibble = reg_PC[addr_nibble_ptr*4+:4];
@ -227,7 +227,7 @@ always @(posedge i_clk) begin
*
*/
if (!i_debug_cycle && just_reset && i_phases[3]) begin
if (i_clk_en && just_reset && i_phases[3]) begin
/* this happend right after reset */
if (just_reset) begin
`ifdef SIM
@ -245,7 +245,7 @@ always @(posedge i_clk) begin
end
/* loop to fill the initial PC value in the program */
if (!i_debug_cycle && !control_unit_ready && (bus_prog_addr != 5'b0)) begin
if (i_clk_en && !control_unit_ready && (bus_prog_addr != 5'b0)) begin
/*
* this should load the actual PC values...
*/
@ -273,7 +273,7 @@ always @(posedge i_clk) begin
*
*/
if (!i_debug_cycle && control_unit_ready && !i_bus_busy) begin
if (i_clk_en && control_unit_ready && !i_bus_busy) begin
// `ifdef SIM
// $display("CTRL %0d: [%d] starting to do things", i_phase, i_cycle_ctr);

8
saturn_debugger.v
View file

@ -24,6 +24,7 @@
module saturn_debugger (
i_clk,
i_clk_en,
i_reset,
i_phases,
i_phase,
@ -48,6 +49,7 @@ module saturn_debugger (
);
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
input wire [3:0] i_phases;
input wire [1:0] i_phase;
@ -127,7 +129,7 @@ end
always @(posedge i_clk) begin
if (i_phases[3] && i_instr_decoded) begin
if (i_clk_en && i_phases[3] && i_instr_decoded) begin
$display("DEBUGGER %0d: [%d] start debugger cycle", i_phase, i_cycle_ctr);
o_debug_cycle <= 1'b1;
counter <= 9'd0;
@ -212,12 +214,12 @@ always @(posedge i_clk) begin
registers_ctr <= registers_ctr + 9'd1;
end
if (o_debug_cycle && debug_done && !write_out) begin
if (i_clk_en && o_debug_cycle && debug_done && !write_out) begin
$display("DEBUGGER %0d: [%d] end debugger cycle", i_phase, i_cycle_ctr);
write_out <= 1'b1;
end
if (write_out) begin
if (i_clk_en && write_out) begin
o_char_to_send <= registers_str[counter];
counter <= counter + 9'd1;
`ifdef SIM

6
saturn_hp48gx_rom.v
View file

@ -30,6 +30,7 @@
module saturn_hp48gx_rom (
i_clk,
i_clk_en,
i_reset,
i_phase,
i_cycle_ctr,
@ -41,6 +42,7 @@ module saturn_hp48gx_rom (
);
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
input wire [1:0] i_phase;
input wire [31:0] i_cycle_ctr;
@ -72,7 +74,7 @@ end
wire [0:0] do_pc_read = (last_cmd == `BUSCMD_PC_READ);
wire [0:0] do_dp_read = (last_cmd == `BUSCMD_DP_READ);
wire [0:0] do_read = do_pc_read || do_dp_read;
wire [0:0] can_read = i_bus_clk_en && i_bus_is_data && do_read;
wire [0:0] can_read = i_bus_clk_en && i_clk_en && i_bus_is_data && do_read;
wire [19:0] access_pointer = do_pc_read?local_pc:local_dp;
@ -92,7 +94,7 @@ wire [3:0] imm_nibble = rom_data[address];
*/
always @(posedge i_clk) begin
if (i_bus_clk_en) begin
if (i_bus_clk_en && i_clk_en) begin
if (i_bus_is_data) begin
/* do things with the bits...*/
case (last_cmd)

10
saturn_inst_decoder.v
View file

@ -24,12 +24,12 @@
module saturn_inst_decoder (
i_clk,
i_clk_en,
i_reset,
i_phases,
i_phase,
i_cycle_ctr,
i_debug_cycle,
i_bus_busy,
i_nibble,
@ -53,11 +53,11 @@ module saturn_inst_decoder (
);
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
input wire [3:0] i_phases;
input wire [1:0] i_phase;
input wire [31:0] i_cycle_ctr;
input wire [0:0] i_debug_cycle;
input wire [0:0] i_bus_busy;
@ -151,13 +151,13 @@ always @(posedge i_clk) begin
* either talking to the bus, or debugging something
*/
if (!i_debug_cycle && i_bus_busy && i_phases[2] && just_reset) begin
if (i_clk_en && i_bus_busy && i_phases[2] && just_reset) begin
// $display("DECODER %0d: [%d] dump registers right after reset", i_phase, i_cycle_ctr);
just_reset <= 1'b0;
o_instr_decoded <= 1'b1;
end
if (!i_debug_cycle && !i_bus_busy) begin
if (i_clk_en && !i_bus_busy) begin
if (i_phases[1] && !decode_started) begin
// $display("DECODER %0d: [%d] store current PC as instruction start %5h", i_phase, i_cycle_ctr, i_current_pc);

6
saturn_regs_pc_rstk.v
View file

@ -22,11 +22,11 @@
module saturn_regs_pc_rstk (
i_clk,
i_clk_en,
i_reset,
i_phases,
i_phase,
i_cycle_ctr,
i_debug_cycle,
i_bus_busy,
@ -37,11 +37,11 @@ module saturn_regs_pc_rstk (
);
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
input wire [3:0] i_phases;
input wire [1:0] i_phase;
input wire [31:0] i_cycle_ctr;
input wire [0:0] i_debug_cycle;
input wire [0:0] i_bus_busy;
@ -84,7 +84,7 @@ always @(posedge i_clk) begin
// if (!i_debug_cycle)
// $display("PC_RSTK %0d: [%d] !i_bus_busy %b", i_phase, i_cycle_ctr, !i_bus_busy);
if (!i_debug_cycle && !i_bus_busy) begin
if (i_clk_en && !i_bus_busy) begin
if (i_phases[3] && just_reset) begin
$display("PC_RSTK %0d: [%d] exit from reset mode", i_phase, i_cycle_ctr);

50
saturn_top.v
View file

@ -45,12 +45,13 @@ assign reset = btn[0];
saturn_bus main_bus (
`ifdef SIM
.i_clk (clk),
.i_clk (clk),
`else
.i_clk (clk_25mhz),
.i_clk (clk_25mhz),
`endif
.i_reset (reset),
.o_halt (halt),
.i_clk_en (clk_en),
.i_reset (reset),
.o_halt (halt),
.o_char_to_send (led)
);
@ -78,5 +79,46 @@ always
#10 clk = (clk === 1'b0);
`endif
`ifndef SIM
`define DELAY_BITS 25
`define DELAY_ZERO {`DELAY_BITS{1'b0}}
`define DELAY_ONE {{`DELAY_BITS-1{1'b0}},1'b1}
reg [`DELAY_BITS-1:0] delay;
`endif
reg [0:0] clk_en;
initial begin
`ifdef SIM
clk_en = 1'b1;
`else
delay = `DELAY_ZERO;
clk_en = 1'b0;
`endif
end
always @(posedge clk) begin
`ifndef SIM
delay <= delay + `DELAY_ONE;
if (delay[`DELAY_BITS-1]) begin
clk_en <= 1'b1;
end
if (clk_en) begin
clk_en <= 1'b0;
delay <= `DELAY_ZERO;
end
`endif
if (reset) begin
`ifdef SIM
clk_en <= 1'b1;
`else
delay <= `DELAY_ZERO;
clk_en <= 1'b0;
`endif
end
end
endmodule