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  • bb0654126a add more jump code (hairy) master Raphael Jacquot 2019-09-02 13:20:50 +0200
  • 6fcf04a5c0 fix bus debugger for read program Raphael Jacquot 2019-03-18 07:33:52 +0100
  • dd9faf509e initialize ram with random crap Raphael Jacquot 2019-03-18 07:33:24 +0100
  • 30ae63dfdf add block 13x Raphael Jacquot 2019-03-18 06:54:39 +0100
  • c48944623d implement RTN Raphael Jacquot 2019-03-15 21:38:28 +0100
  • 1771536ca0 implement block_15x Raphael Jacquot 2019-03-15 20:42:51 +0100
  • c953bc82f4 add block Cx and Fx implement 2CMPL and ADD Raphael Jacquot 2019-03-15 17:17:19 +0100
  • e6e3bb2325 add a command line to test UM5G-85K chip Raphael Jacquot 2019-03-15 14:54:24 +0100
  • 35381d5405 pipeline system ram read & writes Raphael Jacquot 2019-03-15 14:27:58 +0100
  • b96dcd717c cleanups pipeline reading from the system ram Raphael Jacquot 2019-03-15 13:50:23 +0100
  • 194415a6ed cleanups Raphael Jacquot 2019-03-15 13:31:37 +0100
  • 2bde756bfe add the sysram module Raphael Jacquot 2019-03-15 12:26:26 +0100
  • d1cb911c5c properly state when the mmio is unconfigured Raphael Jacquot 2019-03-15 12:26:09 +0100
  • 2d43dc67b7 add the rest of the pointer registers loading instructions Raphael Jacquot 2019-03-15 12:25:47 +0100
  • 12f542441d pipeline rstk_ptr calculations for push Raphael Jacquot 2019-03-15 11:35:33 +0100
  • e1aa24d006 fix MHZ->MHz unit Raphael Jacquot 2019-03-15 11:29:27 +0100
  • 81860700c0 add defaults to case, verilator complained Raphael Jacquot 2019-03-15 10:53:14 +0100
  • 7b64f3e297 implement GOSUB (7xxx) Raphael Jacquot 2019-03-15 10:21:02 +0100
  • e9e7a6a5f0 add nice message for rom on CONFIGURE command Raphael Jacquot 2019-03-15 10:20:21 +0100
  • 175c1a48d0 major surgery, add memory read and write back in Raphael Jacquot 2019-03-15 07:15:45 +0100
  • f572107227 add some timing to the compile script Raphael Jacquot 2019-03-15 07:15:26 +0100
  • b3bc8cf327 add a comment about potential slowness Raphael Jacquot 2019-03-15 07:13:38 +0100
  • 2a4d684d0e fis typo Raphael Jacquot 2019-03-15 07:13:20 +0100
  • 3932d6e1f5 added the code for memory read & write, but it's not enabled yet Raphael Jacquot 2019-03-14 23:07:42 +0100
  • a1b22269b2 add mmio fix rtn instructions decode block 14x Raphael Jacquot 2019-03-14 22:20:03 +0100
  • b2ae484450 implement the ALU as it should be Raphael Jacquot 2019-03-14 21:47:05 +0100
  • 137d9b3b5a change compile script to optimize for 50Mhz Raphael Jacquot 2019-03-14 18:05:31 +0100
  • a533e4ea37 cleanup the startup procedure Raphael Jacquot 2019-03-14 17:52:03 +0100
  • 9c05be1152 remove useless crud about the ULX3S Raphael Jacquot 2019-03-14 16:39:20 +0100
  • c62d562008 make it so that execution of bus programs happen in the same cycle as the instruction modify the way jump and rtn are handled add some registers to the debugger Raphael Jacquot 2019-03-14 16:37:51 +0100
  • e97ec2243f pipelining of reading from rom Raphael Jacquot 2019-03-14 14:33:28 +0100
  • c30b96d1af fix an unused warning Raphael Jacquot 2019-03-14 13:49:38 +0100
  • 5f4a8ca8bd more fixes Raphael Jacquot 2019-03-14 13:47:09 +0100
  • 35823428e7 other verilator fixes Raphael Jacquot 2019-03-14 13:45:14 +0100
  • ef93420950 first verilator error fixes Raphael Jacquot 2019-03-14 13:33:07 +0100
  • d808e636c2 add script to run verilator Raphael Jacquot 2019-03-14 13:32:50 +0100
  • 66bcb23d2c fix gitignore Raphael Jacquot 2019-03-14 13:22:15 +0100
  • 9549b53edc implement bus trasfers debugging Raphael Jacquot 2019-03-06 18:19:02 +0100
  • 6d940c7f95 fix the conditions for the debugger to spew chars aout Raphael Jacquot 2019-03-06 14:41:18 +0100
  • e09ed6bc28 udate makefile Raphael Jacquot 2019-03-06 12:49:01 +0100
  • f86a1d03c5 implement base alu functionnality Raphaël Jacquot 2019-03-06 12:16:34 +0100
  • 98b3ed1b79 decode Aax and Abx Raphael Jacquot 2019-03-05 07:56:33 +0100
  • f12a74a917 print a "." when the bus is active, but not reading Raphael Jacquot 2019-03-05 06:47:02 +0100
  • ddae7f9332 start implementing block Axx Raphaël Jacquot 2019-03-05 06:26:33 +0100
  • f3d1a4d9d4 implement D0=(5) Raphaël Jacquot 2019-03-05 06:14:38 +0100
  • 28483afe9a implement CONFIG and RTN* (0[0-3]) Raphaël Jacquot 2019-03-05 05:39:34 +0100
  • 9168cbc1a2 victory, this works on the fpga \o/ using "=" instead of "<=" is evil ! make the fpga halt when necessary Raphael Jacquot 2019-03-04 22:48:09 +0100
  • 4d578f8f18 ok, we're getting somewhere Raphael Jacquot 2019-03-04 21:10:12 +0100
  • 7e0f4a9c0f change the way clk_en is generated Raphaël Jacquot 2019-03-04 19:59:00 +0100
  • f502451548 update debugger Raphael Jacquot 2019-03-04 19:15:44 +0100
  • 6964b72df1 ok. serial sort of works, except it doesn't... Raphael Jacquot 2019-03-04 18:29:00 +0100
  • 6f3f3ce73c debug the seial port Raphael Jacquot 2019-03-04 17:01:59 +0100
  • dc927031e4 cleanups and simplifications Raphael Jacquot 2019-03-04 15:44:51 +0100
  • ae164feb19 there, serial port works at 115200 needed to add \r,.. Raphael Jacquot 2019-03-04 15:24:05 +0100
  • fcea35b4cb oops, LSB first Raphael Jacquot 2019-03-04 15:15:11 +0100
  • 5716904ac8 add the serial port to the complie change speed to 115200 Raphael Jacquot 2019-03-04 14:53:48 +0100
  • 7708d7a85c attached serial port tentative Raphaël Jacquot 2019-03-04 14:40:31 +0100
  • d87eb7786c add an extra script Raphael Jacquot 2019-03-04 13:44:37 +0100
  • 383841f89a make it yet faster Raphael Jacquot 2019-03-04 13:29:03 +0100
  • 479382e004 export rstk_ptr to debugger implement LCHEX (and almost done for LAHEX) Raphaël Jacquot 2019-03-04 13:28:08 +0100
  • e47f12f1d7 implement push PC to RSTK Raphaël Jacquot 2019-03-04 11:52:05 +0100
  • 908b96df6f implement CLRHST and variants implement SET[HEX|DEC] Raphaël Jacquot 2019-03-04 10:53:37 +0100
  • 735504d2b3 implement RESET instruction Raphaël Jacquot 2019-03-04 10:15:37 +0100
  • dd16719a42 recognize PC_READ command Raphaël Jacquot 2019-03-04 10:15:27 +0100
  • c20c893234 replace X with ? to make a difference Raphaël Jacquot 2019-03-04 10:15:11 +0100
  • 8a631c28c2 fix missing bus state reset Raphaël Jacquot 2019-03-04 10:14:44 +0100
  • 18a56d750b export main registers to debugger add C register implement C=P n add dumping C register Raphaël Jacquot 2019-03-04 09:58:13 +0100
  • 7c313c3b5d make it faster yet Raphael Jacquot 2019-03-04 08:56:26 +0100
  • b2811e82eb too shlow now bus halt in simulation only Raphael Jacquot 2019-03-04 08:44:05 +0100
  • 12173e72c4 fix forgotten reset slow it down some Raphael Jacquot 2019-03-04 08:32:34 +0100
  • 39182feaf1 fix miscalculations and typo Raphael Jacquot 2019-03-04 08:23:53 +0100
  • 5968e6f00e 1/32s is too fast ;-) Raphael Jacquot 2019-03-04 08:16:27 +0100
  • e0eecde066 merge Raphaël Jacquot 2019-03-04 08:10:53 +0100
  • 009f01f5d7 implement 8[45]x ST=[01] n implement GOVLNG dump 2 lines of registers in debugger now Raphaël Jacquot 2019-03-04 08:08:02 +0100
  • 8cbf9f59a2 make the blinkenlights pretty Raphael Jacquot 2019-03-03 23:24:50 +0100
  • da3cce2c07 execute the first jump successfully, and start reading the next instruction Raphaël Jacquot 2019-03-03 22:38:56 +0100
  • a301036968 Merge branch 'master' of github.com:sxpert/hp-saturn Raphaël Jacquot 2019-03-03 20:49:10 +0100
  • 631b7f9153 start implementing jump instructions Raphaël Jacquot 2019-03-03 20:48:56 +0100
  • d17a4eb533 cleanup Raphaël Jacquot 2019-03-03 20:48:48 +0100
  • cfd7603e96 we have signal ! Raphael Jacquot 2019-03-03 18:22:48 +0100
  • c04c770cba successfully got the saturn to startup on the ECP5 \o/ Raphael Jacquot 2019-03-03 17:29:30 +0100
  • bc25d4a61a cleanup blinky test Raphael Jacquot 2019-03-03 16:18:30 +0100
  • 42e49caca3 cleanup of top Raphael Jacquot 2019-03-03 15:59:02 +0100
  • e192444f51 added a chaser to test the board Raphael Jacquot 2019-03-03 15:46:21 +0100
  • 6dd38500a8 add a counter to slow things down Raphaël Jacquot 2019-03-03 15:19:07 +0100
  • ca29b542c3 there, a working compile shell script Raphael Jacquot 2019-03-03 14:16:58 +0100
  • 531e0cab02 update compile file Raphael Jacquot 2019-03-03 14:00:10 +0100
  • 28a81503eb store current PC for the currently decoding instruction Raphaël Jacquot 2019-03-03 13:34:00 +0100
  • b58be38b10 connect debugger to leds Raphaël Jacquot 2019-03-03 13:33:32 +0100
  • a6d5491619 fix the compilation for proper use of clk_25mhz signal as clock Raphael Jacquot 2019-03-03 13:03:36 +0100
  • 9cb1618acb fix the rom module for proper bram generation Raphael Jacquot 2019-03-03 13:03:12 +0100
  • 391e5b6e93 change address bits to 12 (4096*4) Raphaël Jacquot 2019-03-03 10:27:31 +0100
  • ae17cd1361 cleanup the rom Raphael Jacquot 2019-03-03 10:24:53 +0100
  • 2cab45a6ff remove the reset on the rom access, doesn't work Raphaël Jacquot 2019-03-03 10:08:26 +0100
  • 7e4ab90369 merge a few wire and assigns... can't do it on port declarations though Raphael Jacquot 2019-03-03 09:47:28 +0100
  • 61957fab3e fix misplaced ifdef discover you can directly set contents of a wire without requiring an assign Raphael Jacquot 2019-03-03 09:43:18 +0100
  • eeb5150159 add the beginnings of a PC and RSTK handler fix bad maths in the rom-gx-r module wire in the PC in the debugger and the control unit add an execute flag, to start execution of partially decoded instructions that need reading data from the instruction stream Raphaël Jacquot 2019-03-03 09:33:42 +0100
  • 6c371cf203 increase ROMBITS to fully utilize one memory block Raphaël Jacquot 2019-03-03 08:09:33 +0100
  • 8fb7ad0eac try async version of reading rom... inconclusive Raphael Jacquot 2019-03-03 08:03:43 +0100
  • 3347a9702d add display of the carry Raphaël Jacquot 2019-03-03 07:45:03 +0100