attached serial port tentative

run.sh

@@ -11,7 +11,7 @@
 # fi
 #iverilog -v -Wall -DSIM -o mask_gen_tb mask_gen.v
 iverilog -v -Wall -DSIM -o z_saturn_test.iv -s saturn_top \
-    saturn_top.v \
+    saturn_top.v saturn_serial.v \
     saturn_bus.v saturn_hp48gx_rom.v \
     saturn_bus_controller.v saturn_debugger.v \
     saturn_control_unit.v saturn_inst_decoder.v \

saturn_bus.v

@@ -27,7 +27,9 @@ module saturn_bus (
     o_halt,
     o_phase,
     o_cycle_ctr,
-    o_char_to_send
+    o_char_to_send,
+    o_char_valid,
+    i_serial_busy
 );
 
 input  wire [0:0]  i_clk;
@@ -37,6 +39,8 @@ output wire [0:0]  o_halt;
 output wire [1:0]  o_phase;
 output wire [31:0] o_cycle_ctr;
 output wire [7:0]  o_char_to_send;
+output wire [0:0]  o_char_valid;
+input  wire [0:0]  i_serial_busy;
 
 assign o_phase = phase;
 assign o_cycle_ctr = cycle_ctr;
@@ -87,6 +91,8 @@ saturn_bus_controller bus_controller (
 
     .o_debug_cycle      (dbg_debug_cycle),
     .o_char_to_send     (o_char_to_send),
+    .o_char_valid       (o_char_valid),
+    .i_serial_busy      (i_serial_busy),
     .o_halt             (ctrl_halt)
 );
 

saturn_bus_controller.v

@@ -35,6 +35,8 @@ module saturn_bus_controller (
 
     o_debug_cycle,
     o_char_to_send,
+    o_char_valid,
+    i_serial_busy,
     o_halt
 );
 
@@ -52,6 +54,8 @@ input  wire [3:0]  i_bus_nibble_in;
 
 output wire [0:0]  o_debug_cycle;
 output wire [7:0]  o_char_to_send;
+output wire [0:0]  o_char_valid;
+input  wire [0:0]  i_serial_busy;
 output wire [0:0]  o_halt;
 
 /**************************************************************************************************
@@ -165,7 +169,9 @@ saturn_debugger debugger (
     .i_instr_type      (dec_instr_type),
     .i_instr_decoded   (dec_instr_decoded),
 
-    .o_char_to_send    (o_char_to_send)
+    .o_char_to_send    (o_char_to_send),
+    .o_char_valid      (o_char_valid),
+    .i_serial_busy     (i_serial_busy)
 );
 
 wire [4:0] dbg_register;

saturn_debugger.v

@@ -57,7 +57,9 @@ module saturn_debugger (
     i_instr_decoded,
 
     /* output to leds */
-    o_char_to_send
+    o_char_to_send,
+    o_char_valid,
+    i_serial_busy
 );
 
 input  wire [0:0]  i_clk;
@@ -94,6 +96,8 @@ input  wire [3:0]  i_instr_type;
 input  wire [0:0]  i_instr_decoded;
 
 output reg  [7:0]  o_char_to_send;
+output reg  [0:0]  o_char_valid;
+input  wire [0:0]  i_serial_busy;
 
 /**************************************************************************************************
  *
@@ -143,6 +147,7 @@ initial begin
     registers_reg_ptr = 6'b0;
     o_dbg_register    = `ALU_REG_NONE;
     registers_done    = 1'b0;
+    o_char_valid      = 1'b0;
     carry = 1'b1;
 end
 
@@ -492,8 +497,10 @@ always @(posedge i_clk) begin
         write_out <= 1'b1;
     end
 
-    if (i_clk_en && write_out) begin
+    /* writes the chars to the serial port */
+    if (i_clk_en && write_out && !o_char_valid && !i_serial_busy) begin
         o_char_to_send <= registers_str[counter];
+        o_char_valid   <= 1'b1;
         counter <= counter + 9'd1;
 `ifdef SIM
         $write("%c", registers_str[counter]);
@@ -508,6 +515,10 @@ always @(posedge i_clk) begin
             o_debug_cycle  <= 1'b0;
         end
     end
+    /* clear the char clock enable */
+    if (write_out && o_char_valid) begin
+        o_char_valid <= 1'b0;
+    end
 
     if (i_reset) begin
         o_debug_cycle     <= 1'b0;
@@ -518,6 +529,7 @@ always @(posedge i_clk) begin
         o_dbg_register    <= `ALU_REG_NONE;
         registers_done    <= 1'b0;
         write_out         <= 1'b0;
+        o_char_valid      <= 1'b0;
     end
 
 end

saturn_serial.v

@@ -0,0 +1,86 @@
+/*
+    (c) Raphaël Jacquot 2019
+    
+		This file is part of hp_saturn.
+
+    hp_saturn is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    any later version.
+
+    hp_saturn is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Foobar.  If not, see <https://www.gnu.org/licenses/>.
+
+ */
+
+`default_nettype none
+
+module saturn_serial (
+    i_clk,
+
+    i_char_to_send,
+    i_char_valid,
+
+    o_serial_tx,
+
+    o_serial_busy
+);
+
+input  wire [0:0]  i_clk;
+
+input  wire [7:0]  i_char_to_send;
+input  wire [0:0]  i_char_valid;
+
+output wire [0:0]  o_serial_tx;
+
+output wire [0:0]  o_serial_busy;
+
+/*
+ *
+ */
+
+reg  [9:0]  clocking_reg;
+reg  [9:0]  data_reg;
+
+`ifdef SIM
+`define BIT_DELAY_START 13'h0
+`define BIT_DELAY_TEST  0
+`else
+`define BIT_DELAY_START 13'h54D
+`define BIT_DELAY_TEST  12
+`endif
+
+reg  [12:0] bit_delay;
+
+initial begin
+    bit_delay    <= `BIT_DELAY_START;
+    clocking_reg <= {10{1'b1}};
+    data_reg     <= {10{1'b1}};
+end
+
+assign o_serial_busy = !clocking_reg[9];
+assign o_serial_tx   = data_reg[9];
+
+always @(posedge i_clk) begin
+    // $display("%0d", bit_delay);
+    if (i_char_valid && !o_serial_busy) begin
+        $display("serial storing char %c", i_char_to_send);
+        clocking_reg <= 10'b0;
+        data_reg     <= { 1'b0, i_char_to_send, 1'b1 };
+        bit_delay    <= `BIT_DELAY_START;
+    end
+    if (!i_char_valid && o_serial_busy && bit_delay[`BIT_DELAY_TEST]) begin
+        $display("%b %b", o_serial_tx, data_reg);
+        clocking_reg <= { clocking_reg[8:0], 1'b1};
+        data_reg     <= { data_reg[8:0],     1'b1};
+        bit_delay    <= `BIT_DELAY_START;
+    end
+    bit_delay    <= bit_delay + 13'd1;
+end
+
+endmodule

saturn_top.v

@@ -28,10 +28,22 @@ saturn_bus main_bus (
     .i_clk_en       (clk_en),
     .i_reset        (reset),
     .o_halt         (halt),
-    .o_char_to_send (t_led)
+    .o_char_to_send (char_to_send),
+    .o_char_valid   (char_valid),
+    .i_serial_busy  (serial_busy)
 );
 
-wire [7:0] t_led;
+saturn_serial serial_port (
+    .i_clk          (clk),
+    .i_char_to_send (char_to_send),
+    .i_char_valid   (char_valid),
+    .o_serial_busy  (serial_busy)
+);
+
+wire [7:0] char_to_send;
+wire [0:0] char_valid;
+wire [0:0] serial_busy;
+
 wire [7:0]  led;
 reg  [0:0] reset;
 wire [0:0] halt;
@@ -85,13 +97,15 @@ module saturn_top (
 	clk_25mhz,
 	btn,
 	led,
-    wifi_gpio0
+    wifi_gpio0,
+    ftdi_rxd
 );
 
 input  wire [0:0] clk_25mhz;
 input  wire [6:0] btn;
 output reg  [7:0] led;
 output wire [0:0] wifi_gpio0;
+output wire [0:0] ftdi_rxd;
 
 /* this is necessary, otherwise, the esp32 module reboots the fpga in passthrough */
 assign wifi_gpio0 = btn[0];
@@ -103,7 +117,17 @@ saturn_bus main_bus (
     .o_halt         (halt),
     .o_phase        (phase),
     .o_cycle_ctr    (cycle_ctr),
-    .o_char_to_send (t_led)
+    .o_char_to_send (char_to_send),
+    .o_char_valid   (char_valid),
+    .i_serial_busy  (serial_busy)
+);
+
+saturn_serial serial_port (
+    .i_clk          (clk_25mhz),
+    .i_char_to_send (char_to_send),
+    .i_char_valid   (char_valid),
+    .o_serial_tx    (ftdi_rxd),
+    .o_serial_busy  (serial_busy)
 );
 
 reg  [25:0] delay;
@@ -113,7 +137,9 @@ reg  [0:0]  reset;
 wire [0:0]  halt;
 wire [1:0]  phase;
 wire [31:0] cycle_ctr;
-wire [7:0]  t_led;
+wire [7:0]  char_to_send;
+wire [0:0]  char_valid;
+wire [0:0]  serial_busy;
 
 
 /* 1/4 s */
@@ -154,7 +180,7 @@ always @(posedge clk_25mhz) begin
 
     if (clk2 && !halt) begin
         clk_en <= 1'b1;
-        led    <= t_led;
+        led    <= char_to_send;
     end
 
     if (clk_en)