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export main registers to debugger

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add C register
implement C=P n
add dumping C register
This commit is contained in:
Raphaël Jacquot 2019-03-04 09:58:13 +01:00
parent 7c313c3b5d
commit 18a56d750b
6 changed files with 169 additions and 6 deletions
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2
saturn_bus.v
View file

@ -147,7 +147,7 @@ always @(posedge i_clk) begin
end
`ifdef SIM
if (cycle_ctr == 53) begin
if (cycle_ctr == 60) begin
bus_halt <= 1'b1;
$display("BUS %0d: [%d] enough cycles for now", phase, cycle_ctr);
end

13
saturn_bus_controller.v
View file

@ -83,6 +83,10 @@ saturn_control_unit control_unit (
.o_reg_st (ctrl_reg_st),
.o_reg_p (ctrl_reg_p),
.i_dbg_register (dbg_register),
.i_dbg_reg_ptr (dbg_reg_ptr),
.o_dbg_reg_nibble (ctrl_reg_nibble),
.o_alu_reg_dest (dec_alu_reg_dest),
.o_alu_reg_src_1 (dec_alu_reg_src_1),
.o_alu_reg_src_2 (dec_alu_reg_src_2),
@ -104,6 +108,8 @@ wire [3:0] ctrl_reg_hst;
wire [15:0] ctrl_reg_st;
wire [3:0] ctrl_reg_p;
wire [3:0] ctrl_reg_nibble;
wire [4:0] dec_alu_reg_dest;
wire [4:0] dec_alu_reg_src_1;
wire [4:0] dec_alu_reg_src_2;
@ -135,6 +141,10 @@ saturn_debugger debugger (
.i_reg_st (ctrl_reg_st),
.i_reg_p (ctrl_reg_p),
.o_dbg_register (dbg_register),
.o_dbg_reg_ptr (dbg_reg_ptr),
.i_dbg_reg_nibble (ctrl_reg_nibble),
.i_alu_reg_dest (dec_alu_reg_dest),
.i_alu_reg_src_1 (dec_alu_reg_src_1),
.i_alu_reg_src_2 (dec_alu_reg_src_2),
@ -147,6 +157,9 @@ saturn_debugger debugger (
.o_char_to_send (o_char_to_send)
);
wire [4:0] dbg_register;
wire [3:0] dbg_reg_ptr;
wire [0:0] dbg_debug_cycle;
assign o_debug_cycle = dbg_debug_cycle;

42
saturn_control_unit.v
View file

@ -48,6 +48,10 @@ module saturn_control_unit (
o_reg_p,
o_reg_hst,
o_reg_st,
/* register access */
i_dbg_register,
i_dbg_reg_ptr,
o_dbg_reg_nibble,
o_alu_reg_dest,
o_alu_reg_src_1,
@ -84,7 +88,11 @@ output wire [19:0] o_current_pc;
output wire [3:0] o_reg_p;
output wire [3:0] o_reg_hst;
output wire [15:0] o_reg_st;
/* register access */
input wire [4:0] i_dbg_register;
input wire [3:0] i_dbg_reg_ptr;
output reg [3:0] o_dbg_reg_nibble;
output wire [4:0] o_alu_reg_dest;
output wire [4:0] o_alu_reg_src_1;
output wire [4:0] o_alu_reg_src_2;
@ -168,15 +176,22 @@ wire [0:0] dec_error;
wire [0:0] inst_alu = (dec_instr_type == `INSTR_TYPE_ALU);
wire [0:0] inst_jump = (dec_instr_type == `INSTR_TYPE_JUMP);
wire [0:0] reg_dest_c = (dec_alu_reg_dest == `ALU_REG_C);
wire [0:0] reg_dest_st = (dec_alu_reg_dest == `ALU_REG_ST);
wire [0:0] reg_dest_p = (dec_alu_reg_dest == `ALU_REG_P);
wire [0:0] reg_src_1_p = (dec_alu_reg_src_1 == `ALU_REG_P);
wire [0:0] reg_src_1_imm = (dec_alu_reg_src_1 == `ALU_REG_IMM);
wire [0:0] aluop_copy = inst_alu && (dec_alu_opcode == `ALU_OP_COPY);
wire [0:0] inst_alu_p_eq_n = aluop_copy && reg_dest_p && reg_src_1_imm;
wire [0:0] inst_alu_c_eq_p_n = aluop_copy && reg_dest_c && reg_src_1_p;
wire [0:0] inst_alu_st_eq_01_n = aluop_copy && reg_dest_st && reg_src_1_imm;
wire [0:0] inst_alu_other = !(inst_alu_p_eq_n || inst_alu_st_eq_01_n);
wire [0:0] inst_alu_other = !(inst_alu_p_eq_n ||
inst_alu_st_eq_01_n ||
inst_alu_c_eq_p_n);
/**************************************************************************************************
@ -215,12 +230,20 @@ saturn_regs_pc_rstk regs_pc_rstk (
*
*************************************************************************************************/
reg [3:0] reg_C[0:15];
reg [3:0] reg_HST;
reg [15:0] reg_ST;
reg [3:0] reg_P;
wire [19:0] reg_PC;
wire [0:0] reload_PC;
always @(*) begin
case (i_dbg_register)
`ALU_REG_C: o_dbg_reg_nibble <= reg_C[i_dbg_reg_ptr];
default: o_dbg_reg_nibble <= 4'h0;
endcase
end
/**************************************************************************************************
*
* the control unit
@ -229,6 +252,7 @@ wire [0:0] reload_PC;
reg [0:0] control_unit_error;
reg [0:0] just_reset;
reg [3:0] init_counter;
reg [0:0] control_unit_ready;
reg [4:0] bus_program[0:31];
reg [4:0] bus_prog_addr;
@ -245,6 +269,7 @@ initial begin
o_no_read = 1'b0;
control_unit_error = 1'b0;
just_reset = 1'b1;
init_counter = 4'b0;
control_unit_ready = 1'b0;
bus_prog_addr = 5'd0;
addr_nibble_ptr = 3'd0;
@ -258,6 +283,12 @@ end
always @(posedge i_clk) begin
if (just_reset || (init_counter != 0)) begin
$display("CTRL %0d: [%d] initializing registers %0d", i_phase, i_cycle_ctr, init_counter);
reg_C[init_counter] <= 4'b0;
init_counter <= init_counter + 4'b1;
end
/************************
*
* we're just starting, load the PC into the controller and modules
@ -346,6 +377,12 @@ always @(posedge i_clk) begin
reg_P <= dec_alu_imm_value;
end
/* 80Cn C=P n */
if (inst_alu_c_eq_p_n) begin
reg_C[dec_alu_ptr_begin] <= reg_P;
end
/* 8[45]n ST=[01] n */
if (inst_alu_st_eq_01_n) begin
$display("CTRL %0d: [%d] exec : ST=%b %h", i_phase, i_cycle_ctr, dec_alu_imm_value[0], dec_alu_ptr_begin);
@ -370,6 +407,7 @@ always @(posedge i_clk) begin
o_no_read <= 1'b0;
control_unit_error <= 1'b0;
just_reset <= 1'b1;
init_counter <= 4'b0;
control_unit_ready <= 1'b0;
bus_prog_addr <= 5'd0;
addr_nibble_ptr <= 3'd0;

41
saturn_debugger.v
View file

@ -21,6 +21,7 @@
`default_nettype none
`include "saturn_def_debugger.v"
`include "saturn_def_alu.v"
module saturn_debugger (
i_clk,
@ -38,6 +39,10 @@ module saturn_debugger (
i_reg_st,
i_reg_p,
o_dbg_register,
o_dbg_reg_ptr,
i_dbg_reg_nibble,
i_alu_reg_dest,
i_alu_reg_src_1,
i_alu_reg_src_2,
@ -66,6 +71,11 @@ input wire [3:0] i_reg_hst;
input wire [15:0] i_reg_st;
input wire [3:0] i_reg_p;
output reg [4:0] o_dbg_register;
output wire [3:0] o_dbg_reg_ptr;
assign o_dbg_reg_ptr = registers_reg_ptr[3:0];
input wire [3:0] i_dbg_reg_nibble;
input wire [4:0] i_alu_reg_dest;
input wire [4:0] i_alu_reg_src_1;
input wire [4:0] i_alu_reg_src_2;
@ -94,7 +104,7 @@ reg [7:0] hex[0:15];
reg [8:0] registers_ctr;
reg [7:0] registers_str[0:511];
reg [4:0] registers_state;
reg [5:0] registers_state;
reg [4:0] registers_reg_ptr;
reg [0:0] registers_done;
@ -123,6 +133,7 @@ initial begin
registers_ctr = 9'd0;
registers_state = `DBG_REG_PC_STR;
registers_reg_ptr = 5'b0;
o_dbg_register = `ALU_REG_NONE;
registers_done = 1'b0;
carry = 1'b1;
end
@ -385,7 +396,32 @@ always @(posedge i_clk) begin
`DBG_REG_NL_1:
begin
registers_str[registers_ctr] <= "\n";
registers_state <= `DBG_REG_END;
registers_state <= `DBG_REG_C_STR;
end
`DBG_REG_C_STR:
begin
case (registers_reg_ptr)
5'd0: registers_str[registers_ctr] <= "C";
5'd1: registers_str[registers_ctr] <= ":";
5'd2: registers_str[registers_ctr] <= " ";
5'd3: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 5'd1;
if (registers_reg_ptr == 5'd3) begin
registers_reg_ptr <= 5'd15;
o_dbg_register <= `ALU_REG_C;
registers_state <= `DBG_REG_C_VALUE;
end
end
`DBG_REG_C_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
registers_reg_ptr <= registers_reg_ptr - 1;
if (registers_reg_ptr == 5'd0) begin
registers_reg_ptr <= 5'd0;
o_dbg_register <= `ALU_REG_NONE;
registers_state <= `DBG_REG_END;
end
end
`DBG_REG_END: begin end
default: begin $display("ERROR, unknown register state %0d", registers_state); end
@ -424,6 +460,7 @@ always @(posedge i_clk) begin
registers_ctr <= 9'd0;
registers_state <= `DBG_REG_PC_STR;
registers_reg_ptr <= 5'b0;
o_dbg_register <= `ALU_REG_NONE;
registers_done <= 1'b0;
write_out <= 1'b0;
end

43
saturn_def_debugger.v
View file

@ -15,6 +15,7 @@
`define DBG_REG_RSTK7_STR 6
`define DBG_REG_RSTK7_VALUE 7
`define DBG_REG_NL_0 8
`define DBG_REG_P 9
`define DBG_REG_HST 10
`define DBG_REG_HST_SPACES 11
@ -25,5 +26,45 @@
`define DBG_REG_RSTK6_VALUE 16
`define DBG_REG_NL_1 17
`define DBG_REG_END 31
`define DBG_REG_A_STR 18
`define DBG_REG_A_VALUE 19
`define DBG_REG_A_SPACES 20
`define DBG_REG_R0_STR 21
`define DBG_REG_R0_VALUE 22
`define DBG_REG_R0_SPACES 23
`define DBG_REG_RSTK5_STR 24
`define DBG_REG_RSTK5_VALUE 25
`define DBG_REG_NL_2 26
`define DBG_REG_B_STR 27
`define DBG_REG_B_VALUE 28
`define DBG_REG_B_SPACES 29
`define DBG_REG_R1_STR 30
`define DBG_REG_R1_VALUE 31
`define DBG_REG_R1_SPACES 32
`define DBG_REG_RSTK4_STR 33
`define DBG_REG_RSTK4_VALUE 34
`define DBG_REG_NL_3 35
`define DBG_REG_C_STR 36
`define DBG_REG_C_VALUE 37
`define DBG_REG_C_SPACES 38
`define DBG_REG_R2_STR 39
`define DBG_REG_R2_VALUE 40
`define DBG_REG_R2_SPACES 41
`define DBG_REG_RSTK3_STR 42
`define DBG_REG_RSTK3_VALUE 43
`define DBG_REG_NL_4 44
`define DBG_REG_D_STR 45
`define DBG_REG_D_VALUE 46
`define DBG_REG_D_SPACES 47
`define DBG_REG_R3_STR 48
`define DBG_REG_R3_VALUE 49
`define DBG_REG_R3_SPACES 50
`define DBG_REG_RSTK2_STR 51
`define DBG_REG_RSTK2_VALUE 52
`define DBG_REG_NL_5 53
`define DBG_REG_END 63
`endif

34
saturn_inst_decoder.v
View file

@ -124,6 +124,8 @@ reg [0:0] decode_started;
reg [0:0] block_2x;
reg [0:0] block_6x;
reg [0:0] block_8x;
reg [0:0] block_80x;
reg [0:0] block_80Cx;
reg [0:0] block_84x_85x;
reg [0:0] block_JUMP;
@ -160,6 +162,8 @@ initial begin
block_2x = 1'b0;
block_6x = 1'b0;
block_8x = 1'b0;
block_80x = 1'b0;
block_80Cx = 1'b0;
block_84x_85x = 1'b0;
block_JUMP = 1'b0;
@ -250,6 +254,7 @@ always @(posedge i_clk) begin
if (block_8x) begin
case (i_nibble)
4'h0: block_80x <= 1'b1;
4'h4, 4'h5:
begin
o_alu_reg_dest <= `ALU_REG_ST;
@ -277,6 +282,33 @@ always @(posedge i_clk) begin
block_8x <= 1'b0;
end
if (block_80x) begin
case (i_nibble)
4'hC: block_80Cx <= 1'b1;
default:
begin
$display("DECODER %0d: [%d] block_80x %h", i_phase, i_cycle_ctr, i_nibble);
o_decoder_error <= 1'b1;
end
endcase
block_80x <= 1'b0;
end
if (block_80Cx) begin
$display("DECODER %0d: [%d] block_80Cx C=P %h", i_phase, i_cycle_ctr, i_nibble);
o_alu_reg_dest <= `ALU_REG_C;
o_alu_reg_src_1 <= `ALU_REG_P;
o_alu_reg_src_2 <= `ALU_REG_NONE;
o_alu_ptr_begin <= i_nibble;
o_alu_ptr_end <= i_nibble;
o_alu_opcode <= `ALU_OP_COPY;
o_instr_type <= `INSTR_TYPE_ALU;
o_instr_decoded <= 1'b1;
o_instr_execute <= 1'b1;
block_80Cx <= 1'b0;
decode_started <= 1'b0;
end
if (block_84x_85x) begin
o_alu_ptr_begin <= i_nibble;
o_alu_ptr_end <= i_nibble;
@ -334,6 +366,8 @@ always @(posedge i_clk) begin
block_2x <= 1'b0;
block_6x <= 1'b0;
block_8x <= 1'b0;
block_80x <= 1'b0;
block_80Cx <= 1'b0;
block_84x_85x <= 1'b0;
block_JUMP <= 1'b0;