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add the rest of the pointer registers loading instructions

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This commit is contained in:
Raphael Jacquot 2019-03-15 12:25:47 +01:00
parent 12f542441d
commit 2d43dc67b7
2 changed files with 5 additions and 4 deletions
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1
saturn_control_unit.v
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@ -604,6 +604,7 @@ always @(posedge i_clk) begin
case (dec_alu_reg_dest)
`ALU_REG_C: reg_C[dec_alu_ptr_begin] <= dec_alu_imm_value;
`ALU_REG_D0: reg_D0[dec_alu_ptr_begin[2:0]] <= dec_alu_imm_value;
`ALU_REG_D1: reg_D1[dec_alu_ptr_begin[2:0]] <= dec_alu_imm_value;
default:
begin
$display("CTRL %0d: [%d] unsupported register for load %0d", i_phase, i_cycle_ctr, dec_alu_reg_dest);

8
saturn_inst_decoder.v
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@ -326,14 +326,14 @@ always @(posedge i_clk) begin
if (block_1x) begin
case (i_nibble)
4'h4: block_14x <= 1'b1;
4'hB:
4'h9, 4'hA, 4'hB, 4'hD, 4'hE, 4'hF:
begin
$display("DECODER %0d: [%d] D)=(5)", i_phase, i_cycle_ctr, i_nibble);
o_alu_reg_dest <= `ALU_REG_D0;
o_alu_reg_dest <= i_nibble[2]?`ALU_REG_D1:`ALU_REG_D0;
o_alu_ptr_begin <= 4'h0;
o_alu_ptr_end <= 4'h4;
o_alu_ptr_end <= { 1'b0, i_nibble[1]&i_nibble[0], i_nibble[1]&!i_nibble[0], i_nibble[1]^i_nibble[0] };
load_counter <= 4'h0;
load_count <= 4'h4;
load_count <= { 1'b0, i_nibble[1]&i_nibble[0], i_nibble[1]&!i_nibble[0], i_nibble[1]^i_nibble[0] };
o_instr_execute <= 1'b1;
block_LOAD <= 1'b1;
end