Miroirs/hp-saturn
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32 commits

Author SHA1 Message Date
Raphael Jacquot
81860700c0 add defaults to case, verilator complained 2019-03-15 10:53:14 +01:00
Raphael Jacquot
a533e4ea37 cleanup the startup procedure 2019-03-14 17:52:03 +01:00
Raphael Jacquot
c62d562008 make it so that execution of bus programs happen 
in the same cycle as the instruction
modify the way jump and rtn are handled
add some registers to the debugger
 2019-03-14 16:37:51 +01:00
Raphael Jacquot
9549b53edc implement bus trasfers debugging 2019-03-06 18:19:02 +01:00
Raphaël Jacquot
f86a1d03c5 implement base alu functionnality 2019-03-06 12:16:34 +01:00
Raphael Jacquot
f12a74a917 print a "." when the bus is active, but not reading 2019-03-05 06:47:02 +01:00
Raphaël Jacquot
f3d1a4d9d4 implement D0=(5) 2019-03-05 06:14:38 +01:00
Raphaël Jacquot
28483afe9a implement CONFIG and RTN* (0[0-3]) 2019-03-05 05:39:34 +01:00
Raphael Jacquot
9168cbc1a2 victory, this works on the fpga \o/ 
using "=" instead of "<=" is evil !
make the fpga halt when necessary
 2019-03-04 22:48:09 +01:00
Raphael Jacquot
4d578f8f18 ok, we're getting somewhere 2019-03-04 21:10:12 +01:00
Raphael Jacquot
f502451548 update debugger 2019-03-04 19:15:44 +01:00
Raphael Jacquot
6964b72df1 ok. serial sort of works, except it doesn't... 2019-03-04 18:29:00 +01:00
Raphael Jacquot
6f3f3ce73c debug the seial port 2019-03-04 17:01:59 +01:00
Raphael Jacquot
dc927031e4 cleanups and simplifications 2019-03-04 15:44:51 +01:00
Raphael Jacquot
ae164feb19 there, serial port works at 115200 
needed to add \r,..
 2019-03-04 15:24:05 +01:00
Raphaël Jacquot
7708d7a85c attached serial port tentative 2019-03-04 14:40:31 +01:00
Raphaël Jacquot
479382e004 export rstk_ptr to debugger 
implement LCHEX (and almost done for LAHEX)
 2019-03-04 13:28:08 +01:00
Raphaël Jacquot
e47f12f1d7 implement push PC to RSTK 2019-03-04 11:52:05 +01:00
Raphaël Jacquot
908b96df6f implement CLRHST and variants 
implement SET[HEX|DEC]
 2019-03-04 10:53:37 +01:00
Raphaël Jacquot
c20c893234 replace X with ? to make a difference 2019-03-04 10:15:11 +01:00
Raphaël Jacquot
18a56d750b export main registers to debugger 
add C register
implement C=P n
add dumping C register
 2019-03-04 09:58:13 +01:00
Raphaël Jacquot
009f01f5d7 implement 8[45]x ST=[01] n 
implement GOVLNG
dump 2 lines of registers in debugger now
 2019-03-04 08:08:02 +01:00
Raphaël Jacquot
6dd38500a8 add a counter to slow things down 2019-03-03 15:19:07 +01:00
Raphaël Jacquot
b58be38b10 connect debugger to leds 2019-03-03 13:33:32 +01:00
Raphaël Jacquot
eeb5150159 add the beginnings of a PC and RSTK handler 
fix bad maths in the rom-gx-r module
wire in the PC in the debugger and the control unit
add an execute flag, to start execution of partially
decoded instructions that need reading data from the
instruction stream
 2019-03-03 09:33:42 +01:00
Raphaël Jacquot
3347a9702d add display of the carry 2019-03-03 07:45:03 +01:00
Raphaël Jacquot
b3d72c1d3b add some more debugging functionnality 
segregate reading of the rom in it's own little world
 2019-03-03 07:25:22 +01:00
Raphaël Jacquot
006b663147 implement hex->ascii conversion with a table 2019-03-03 06:57:14 +01:00
Raphael Jacquot
182623e043 remove char counting aid 2019-03-02 22:48:34 +01:00
Raphaël Jacquot
42e8a146ce start implementing some type of debugging functionnality 2019-03-02 21:45:38 +01:00
Raphaël Jacquot
2fcd9f7b23 decode our first instruction 
execute said instruction
start implementing the debugging engine to see what we are doing
 2019-03-02 19:40:31 +01:00
Raphael Jacquot
8ce2d2a993 implement more of the bus controller 2019-03-02 13:22:09 +01:00