Miroirs/hp-saturn
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Author SHA1 Message Date
Raphael Jacquot
30ae63dfdf add block 13x 2019-03-18 06:54:39 +01:00
Raphael Jacquot
c48944623d implement RTN 2019-03-15 21:38:28 +01:00
Raphael Jacquot
1771536ca0 implement block_15x 2019-03-15 20:42:51 +01:00
Raphael Jacquot
c953bc82f4 add block Cx and Fx 
implement 2CMPL and ADD
 2019-03-15 17:17:19 +01:00
Raphael Jacquot
e6e3bb2325 add a command line to test UM5G-85K chip 2019-03-15 14:54:24 +01:00
Raphael Jacquot
35381d5405 pipeline system ram read & writes 2019-03-15 14:27:58 +01:00
Raphael Jacquot
b96dcd717c cleanups 
pipeline reading from the system ram
 2019-03-15 13:50:23 +01:00
Raphael Jacquot
194415a6ed cleanups 2019-03-15 13:31:37 +01:00
Raphael Jacquot
2bde756bfe add the sysram module 2019-03-15 12:26:26 +01:00
Raphael Jacquot
d1cb911c5c properly state when the mmio is unconfigured 2019-03-15 12:26:09 +01:00
Raphael Jacquot
2d43dc67b7 add the rest of the pointer registers loading instructions 2019-03-15 12:25:47 +01:00
Raphael Jacquot
12f542441d pipeline rstk_ptr calculations for push 2019-03-15 11:35:33 +01:00
Raphael Jacquot
e1aa24d006 fix MHZ->MHz unit 2019-03-15 11:29:27 +01:00
Raphael Jacquot
81860700c0 add defaults to case, verilator complained 2019-03-15 10:53:14 +01:00
Raphael Jacquot
7b64f3e297 implement GOSUB (7xxx) 2019-03-15 10:21:02 +01:00
Raphael Jacquot
e9e7a6a5f0 add nice message for rom on CONFIGURE command 2019-03-15 10:20:21 +01:00
Raphael Jacquot
175c1a48d0 major surgery, add memory read and write back in 2019-03-15 07:15:45 +01:00
Raphael Jacquot
f572107227 add some timing to the compile script 2019-03-15 07:15:26 +01:00
Raphael Jacquot
b3bc8cf327 add a comment about potential slowness 2019-03-15 07:13:38 +01:00
Raphael Jacquot
2a4d684d0e fis typo 2019-03-15 07:13:20 +01:00
Raphael Jacquot
3932d6e1f5 added the code for memory read & write, but it's not enabled yet 2019-03-14 23:07:42 +01:00
Raphael Jacquot
a1b22269b2 add mmio 
fix rtn instructions
decode block 14x
 2019-03-14 22:20:03 +01:00
Raphael Jacquot
b2ae484450 implement the ALU as it should be 2019-03-14 21:47:05 +01:00
Raphael Jacquot
137d9b3b5a change compile script to optimize for 50Mhz 2019-03-14 18:05:31 +01:00
Raphael Jacquot
a533e4ea37 cleanup the startup procedure 2019-03-14 17:52:03 +01:00
Raphael Jacquot
9c05be1152 remove useless crud about the ULX3S 2019-03-14 16:39:20 +01:00
Raphael Jacquot
c62d562008 make it so that execution of bus programs happen 
in the same cycle as the instruction
modify the way jump and rtn are handled
add some registers to the debugger
 2019-03-14 16:37:51 +01:00
Raphael Jacquot
e97ec2243f pipelining of reading from rom 2019-03-14 14:33:28 +01:00
Raphael Jacquot
c30b96d1af fix an unused warning 2019-03-14 13:49:38 +01:00
Raphael Jacquot
5f4a8ca8bd more fixes 2019-03-14 13:47:09 +01:00
Raphael Jacquot
35823428e7 other verilator fixes 2019-03-14 13:45:14 +01:00
Raphael Jacquot
ef93420950 first verilator error fixes 2019-03-14 13:33:07 +01:00
Raphael Jacquot
d808e636c2 add script to run verilator 2019-03-14 13:32:50 +01:00
Raphael Jacquot
66bcb23d2c fix gitignore 2019-03-14 13:22:15 +01:00
Raphael Jacquot
9549b53edc implement bus trasfers debugging 2019-03-06 18:19:02 +01:00
Raphael Jacquot
6d940c7f95 fix the conditions for the debugger to spew chars aout 2019-03-06 14:41:18 +01:00
Raphael Jacquot
e09ed6bc28 udate makefile 2019-03-06 12:49:01 +01:00
Raphaël Jacquot
f86a1d03c5 implement base alu functionnality 2019-03-06 12:16:34 +01:00
Raphael Jacquot
98b3ed1b79 decode Aax and Abx 2019-03-05 07:56:33 +01:00
Raphael Jacquot
f12a74a917 print a "." when the bus is active, but not reading 2019-03-05 06:47:02 +01:00
Raphaël Jacquot
ddae7f9332 start implementing block Axx 2019-03-05 06:26:33 +01:00
Raphaël Jacquot
f3d1a4d9d4 implement D0=(5) 2019-03-05 06:14:38 +01:00
Raphaël Jacquot
28483afe9a implement CONFIG and RTN* (0[0-3]) 2019-03-05 05:39:34 +01:00
Raphael Jacquot
9168cbc1a2 victory, this works on the fpga \o/ 
using "=" instead of "<=" is evil !
make the fpga halt when necessary
 2019-03-04 22:48:09 +01:00
Raphael Jacquot
4d578f8f18 ok, we're getting somewhere 2019-03-04 21:10:12 +01:00
Raphaël Jacquot
7e0f4a9c0f change the way clk_en is generated 2019-03-04 19:59:00 +01:00
Raphael Jacquot
f502451548 update debugger 2019-03-04 19:15:44 +01:00
Raphael Jacquot
6964b72df1 ok. serial sort of works, except it doesn't... 2019-03-04 18:29:00 +01:00
Raphael Jacquot
6f3f3ce73c debug the seial port 2019-03-04 17:01:59 +01:00
Raphael Jacquot
dc927031e4 cleanups and simplifications 2019-03-04 15:44:51 +01:00