Commit graph

293 commits

Author SHA1 Message Date
Raphael Jacquot
92fe235e07 add an instruction counter 2019-02-08 12:46:32 +01:00
Raphael Jacquot
a56f472a45 optimize SETDEC 2019-02-08 11:55:47 +01:00
Raphael Jacquot
0f456bf0af fix more PC handling issues 2019-02-08 11:47:06 +01:00
Raphael Jacquot
5559deab1d fix more PC stuff 2019-02-08 11:15:16 +01:00
Raphael Jacquot
bcf79c9d7d fix handling of PC increments and the like 2019-02-08 11:06:19 +01:00
Raphael Jacquot
90a8a4e9a9 implement more stuff 2019-02-08 00:02:55 +01:00
Raphael Jacquot
24c49893a1 implement more instructions, catch errors 2019-02-07 23:31:35 +01:00
Raphael Jacquot
55bdfed19a entirely redesign the state machine 2019-02-07 22:54:06 +01:00
Raphael Jacquot
4800c6f241 try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
Raphael Jacquot
0940b198d3 remove multiple posedge clk, which doesn't work 2019-02-07 09:38:27 +01:00
Raphael Jacquot
5a5fc9c775 fix all bad warnings 2019-02-07 08:55:41 +01:00
Raphael Jacquot
b5c3a56273 separate reading instructions from reading data 2019-02-07 08:35:59 +01:00
Raphael Jacquot
b519f3d8b3 use a yosys config file instead 2019-02-07 07:11:25 +01:00
Raphael Jacquot
7a1bc5956e add an ifdef 2019-02-07 07:11:11 +01:00
Raphael Jacquot
4c9925c1a3 fix yosys warning 2019-02-07 07:10:33 +01:00
Raphael Jacquot
953323c7b8 rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
Raphael Jacquot
3c32cbc213 attempt to fix bus 2019-02-06 17:50:36 +01:00
Raphael Jacquot
b8fa3b2df0 fix nibble_out in bus 2019-02-06 17:43:14 +01:00
Raphael Jacquot
62b1ab0292 attempt at bus are failing. what am I missing ? 2019-02-06 17:39:25 +01:00
Raphael Jacquot
b0bbacb0cc fix bad assign types 2019-02-06 16:44:52 +01:00
Raphael Jacquot
98ff32e61c make messages for GOTO, GOVLNG and GOSBVL better 2019-02-06 16:14:09 +01:00
Raphael Jacquot
16d9149f1a implement the bus, with priority. currently, only rom and io_ram 2019-02-06 16:04:02 +01:00
Raphael Jacquot
c77b714777 implement some of the bus commands for the io_ram module. 2019-02-06 14:33:44 +01:00
Raphael Jacquot
82f4df8e93 add licence info 2019-02-06 10:40:55 +01:00
Raphael Jacquot
11d3d1dfef add io_ram block (unfinished) 2019-02-05 08:49:14 +01:00
Raphael Jacquot
cc632307ea implement decoding of data transfers 2019-02-05 07:07:19 +01:00
Raphael Jacquot
14272d9978 finish re-coding all instructions 2019-02-04 23:51:36 +01:00
Raphael Jacquot
40d75acc8f implement more stuff 2019-02-04 22:08:17 +01:00
Raphael Jacquot
713689b0f9 fix some verilator warnings 2019-02-04 20:36:47 +01:00
Raphael Jacquot
355539aaaf handle 0 2019-02-04 18:35:53 +01:00
Raphael Jacquot
36fb15a209 add some comments 2019-02-04 18:17:14 +01:00
Raphael Jacquot
59186f6bf8 do more instructions 2019-02-04 18:00:08 +01:00
Raphael Jacquot
d743217132 make it one single process 2019-02-04 17:46:29 +01:00
Raphael Jacquot
d2e7f7d035 commit more stuff 2019-02-04 17:14:08 +01:00
Raphael Jacquot
7fcce53689 implement ST=[01] n 2019-02-04 17:00:08 +01:00
Raphael Jacquot
610647d724 add some ifdefs to hide the various display statements 2019-02-04 16:49:11 +01:00
Raphael Jacquot
5d8fcd41fa transform more pieces (DECODE_8) 2019-02-04 15:48:06 +01:00
Raphael Jacquot
ffaf23b363 handle GOTO in the new form 2019-02-04 15:30:18 +01:00
Raphael Jacquot
9b8428c14c redesigning after people looked at it 2019-02-04 15:02:33 +01:00
Raphael Jacquot
a44c6f6f36 change the way the rom is encoded, makes things easier 2019-02-04 11:31:58 +01:00
Raphael Jacquot
9f0fadf1b1 more changes 2019-02-04 10:55:17 +01:00
Raphael Jacquot
2974a63e02 changed some things from suggestions 2019-02-04 10:38:42 +01:00
Raphael Jacquot
28d4ae60c6 add initial load 2019-02-04 09:59:35 +01:00