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30 commits 1 branch 0 tags 2 MiB
Verilog 99%
Shell 0.7%
Makefile 0.2%
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Raphael Jacquot 7a1bc5956e add an ifdef
2019-02-07 07:11:11 +01:00
.gitignore fix some verilator warnings 2019-02-04 20:36:47 +01:00
bus_commands.v rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
compile rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
empty_lfe5u-85f.config fix some verilator warnings 2019-02-04 20:36:47 +01:00
gen_rom_hex.py add licence info 2019-02-06 10:40:55 +01:00
gxrom-r-decompile implement ST=[01] n 2019-02-04 17:00:08 +01:00
hp48_bus.v rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
hp48_io_ram.v fix yosys warning 2019-02-07 07:10:33 +01:00
hp48_rom.v rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
Makefile implement ST=[01] n 2019-02-04 17:00:08 +01:00
README add licence info 2019-02-06 10:40:55 +01:00
rom-gx-r.hex change the way the rom is encoded, makes things easier 2019-02-04 11:31:58 +01:00
run rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
saturn_core.json rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
saturn_core.v add an ifdef 2019-02-07 07:11:11 +01:00
text.vcd implement ST=[01] n 2019-02-04 17:00:08 +01:00
ulx3s_v20.lpf commit more stuff 2019-02-04 17:14:08 +01:00

README 

Verilog implementation of the HP saturn processor

licence: GPLv3 or later