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fix more PC stuff

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This commit is contained in:
Raphael Jacquot 2019-02-08 11:15:16 +01:00
parent bcf79c9d7d
commit 5559deab1d
14 changed files with 25 additions and 192 deletions
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167
old.v
View file

@ -1,167 +0,0 @@
/****
* Instruction data read
*
*
*/
`define NEXT_INSTR 0
`define NEXT_NIBBLE 1
`define INSTR_START 2
`define INSTR_STROBE 3
`define INSTR_READY 4
`define READ_START 5
`define READ_STROBE 6
`define READ_DONE 7
`define READ_VALUE 8
`define WRITE_START 9
`define WRITE_STROBE 10
`define WRITE_DONE 11
`define RUN_DECODE 12
`define RUN_EXEC 13
`define RUN_INIT 15
case (runstate)
`RUN_INIT:
begin
`ifdef SIM
$display("RUN_INIT => NEXT_INSTR");
`endif
first_nibble <= 0;
first_nibble_ready <= 0;
nibble_ready <= 0;
bus_load_pc <= 1;
runstate <= `NEXT_INSTR;
end
`NEXT_INSTR:
begin
if (bus_load_pc)
begin
bus_address <= PC;
bus_command <= `BUSCMD_LOAD_PC;
bus_load_pc <= 0;
runstate <= `INSTR_START;
end
else
begin
bus_command <= `BUSCMD_PC_READ;
runstate <= `INSTR_STROBE;
end
first_nibble <= 1;
first_nibble_ready <= 0;
nibble_ready <= 0;
saved_PC <= PC;
decstate <= DECODE_START;
`ifdef SIM
// display registers
$display("PC: %05h Carry: %b h: %s rp: %h RSTK7: %05h", PC, Carry, hex_dec?"DEC":"HEX", rstk_ptr, RSTK[7]);
$display("P: %h HST: %b ST: %b RSTK6: %5h", P, HST, ST, RSTK[6]);
$display("A: %h R0: %h RSTK5: %5h", A, R0, RSTK[5]);
$display("B: %h R1: %h RSTK4: %5h", B, R1, RSTK[4]);
$display("C: %h R2: %h RSTK3: %5h", C, R2, RSTK[3]);
$display("D: %h R3: %h RSTK2: %5h", D, R3, RSTK[2]);
$display("D0: %h D1: %h R4: %h RSTK1: %5h", D0, D1, R4, RSTK[1]);
$display(" RSTK0: %5h", RSTK[0]);
`endif
end
`NEXT_NIBBLE: // 1
begin
first_nibble <= 0;
first_nibble_ready <= 0;
nibble_ready <= 0;
end
`INSTR_START: // 2
begin
bus_command <= `BUSCMD_PC_READ;
runstate <= `INSTR_STROBE;
end
`INSTR_STROBE: // 3
begin
bus_command <= `BUSCMD_NOP;
nibble <= bus_nibble_out;
if (first_nibble)
first_nibble_ready <= 1;
else
nibble_ready <= 0;
PC <= PC + 1;
runstate <= `INSTR_READY;
end
`INSTR_READY: // 4
if (decstate == DECODE_START)
begin
//$display("`READ_VALUE -> instruction decoder");
runstate <= `RUN_DECODE;
case (nibble)
4'h0 : decstate <= DECODE_0;
4'h1 : decstate <= DECODE_1;
4'h2 : decstate <= DECODE_P_EQ;
4'h3 : decstate <= DECODE_LC_LEN;
4'h6 : decstate <= DECODE_GOTO;
4'h8 : decstate <= DECODE_8;
4'ha : decstate <= DECODE_A;
default:
begin
`ifdef SIM
$display("%05h nibble %h => unimplemented", saved_PC, nibble);
`endif
decode_error <= 1;
end
endcase
end
`READ_STROBE: // 5
begin
runstate <= `READ_DONE;
end
`READ_DONE: // 6
begin
bus_command <= `BUSCMD_NOP;
nibble <= bus_nibble_out;
PC <= PC + 1;
runstate <= `READ_VALUE;
end
`RUN_DECODE, // C
`RUN_EXEC: // D
begin
end
default:
begin
`ifdef SIM
$display("Unhandled runstate %h in main case statement", runstate);
`endif
end
endcase
//--------------------------------------------------------------------------------------------------
//
// INSTRUCTION DECODING
//
//--------------------------------------------------------------------------------------------------
case (decstate)
`include "opcodes/0x.v"
`include "opcodes/03_RTNCC.v"
`include "opcodes/04_SETHEX.v"
`include "opcodes/05_SETDEC.v"
`include "opcodes/1x.v"
`include "opcodes/1[45]_memaccess_decode.v"
`include "opcodes/1Bnnnnn_D0_EQ_5n.v"
`include "opcodes/2n_P_EQ.v"
`include "opcodes/3n[x...]_LC.v"
`include "opcodes/6xxx_GOTO.v"
`include "opcodes/8x.v"
`include "opcodes/80x.v"
`include "opcodes/805_CONFIG.v"
`include "opcodes/80A_RESET.v"
`include "opcodes/80Cn_C_EQ_P_n.v"
`include "opcodes/82x_CLRHST.v"
`include "opcodes/8[45]n_ST_EQ_[01]_n.v"
`include "opcodes/8[DF]xxxxx_GO.v"
`include "opcodes/A[ab]x.v"
endcase

2
opcodes/03_RTNCC.v
View file

@ -16,6 +16,6 @@ begin
// execute_cycle <= 0;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h RTNCC", saved_PC);
$display("%05h RTNCC", inst_start_PC);
`endif
end

2
opcodes/04_SETHEX.v
View file

@ -12,6 +12,6 @@ begin
// execute_cycle <= 0;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h SETHEX", saved_PC);
$display("%05h SETHEX", inst_start_PC);
`endif
end

2
opcodes/05_SETDEC.v
View file

@ -12,6 +12,6 @@
execute_cycle <= 0;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h SETDEC", saved_PC);
$display("%05h SETDEC", inst_start_PC);
`endif
end

2
opcodes/2n_P_EQ_n.v
View file

@ -10,6 +10,6 @@
P <= nibble;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h P=\t%h", saved_PC, nibble);
$display("%05h P=\t%h", inst_start_PC, nibble);
`endif
end

2
opcodes/3n[x...]_LC.v
View file

@ -16,7 +16,7 @@ end
if (t_ctr == t_cnt) begin
decstate <= `DEC_START;
`ifdef SIM
$write("%5h LC (%h)\t%1h", saved_PC, t_cnt, nibble);
$write("%5h LC (%h)\t%1h", inst_start_PC, t_cnt, nibble);
for(t_ctr = 0; t_ctr != t_cnt; t_ctr ++)
$write("%1h", C[(((t_cnt - t_ctr - 4'h1)+P)%16)*4+:4]);
$write("\n");

2
opcodes/6xxx_GOTO.v
View file

@ -30,6 +30,6 @@ end
execute_cycle <= 0;
decstate <= `DEC_START;
`ifdef SIM
$display("%5h GOTO\t%3h\t=> %05h", saved_PC, jump_offset[11:0], jump_base + jump_offset);
$display("%5h GOTO\t%3h\t=> %05h", inst_start_PC, jump_offset[11:0], jump_base + jump_offset);
`endif
end

2
opcodes/805_CONFIG.v
View file

@ -10,7 +10,7 @@
execute_cycle <= 0;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h CONFIG\t\t\t<= NOT IMPLEMENTED YET", saved_PC);
$display("%05h CONFIG\t\t\t<= NOT IMPLEMENTED YET", inst_start_PC);
`endif
end

2
opcodes/80A_RESET.v
View file

@ -10,6 +10,6 @@
execute_cycle <= 0;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h RESET\t\t\t<= NOT IMPLEMENTED YET", saved_PC);
$display("%05h RESET\t\t\t<= NOT IMPLEMENTED YET", inst_start_PC);
`endif
end

2
opcodes/80Cn_C_EQ_P_n.v
View file

@ -10,6 +10,6 @@
C[nibble*4+:4] <= P;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h C=P\t%h", saved_PC, nibble);
$display("%05h C=P\t%h", inst_start_PC, nibble);
`endif
end

13
opcodes/82x_CLRHST.v
View file

@ -11,13 +11,14 @@
HST <= HST & ~nibble;
decstate <= `DEC_START;
`ifdef SIM
$write("%5h ", inst_start_PC);
case (nibble)
4'h1: $display("%5h XM=0", saved_PC);
4'h2: $display("%5h SB=0", saved_PC);
4'h4: $display("%5h SR=0", saved_PC);
4'h8: $display("%5h MP=0", saved_PC);
4'hf: $display("%5h CLRHST", saved_PC);
default: $display("%5h CLRHST %f", saved_PC, nibble);
4'h1: $display("XM=0");
4'h2: $display("SB=0");
4'h4: $display("SR=0");
4'h8: $display("MP=0");
4'hf: $display("CLRHST");
default: $display("CLRHST\t%f", nibble);
endcase
`endif
end

4
opcodes/8[45]n_ST_EQ_[01]_n.v
View file

@ -9,13 +9,13 @@
ST[nibble] <= 0;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h ST=0\t%h", saved_PC, nibble);
$display("%05h ST=0\t%h", inst_start_PC, nibble);
`endif
end
`DEC_ST_EQ_1_N: begin
ST[nibble] <= 1;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h ST=1\t%h", saved_PC, nibble);
$display("%05h ST=1\t%h", inst_start_PC, nibble);
`endif
end

6
opcodes/8[DF]xxxxx_GO.v
View file

@ -25,15 +25,15 @@ end
end else t_ctr <= t_ctr + 1;
end
`DEC_GOVLNG_EXEC, `DEC_GOSBVL_EXEC: begin
$display("GOSBVL new_PC %5h", new_PC);
$display("GOSBVL PC %5h", PC);
// $display("GOSBVL new_PC %5h", new_PC);
// $display("GOSBVL PC %5h", PC);
if (decstate == `DEC_GOSBVL_EXEC) RSTK[rstk_ptr] <= new_PC;
new_PC <= jump_base;
bus_load_pc <= 1;
execute_cycle <= 0;
decstate <= `DEC_START;
`ifdef SIM
$write("%5h GO", saved_PC);
$write("%5h GO", inst_start_PC);
case (decstate)
`DEC_GOVLNG_EXEC: $write("VLNG");
`DEC_GOSBVL_EXEC: $write("SBVL");

9
saturn_core.v
View file

@ -102,7 +102,7 @@ reg rom_enable;
// internal registers
reg [3:0] nibble;
reg [19:0] new_PC;
reg [19:0] saved_PC;
reg [19:0] inst_start_PC;
reg [2:0] rstk_ptr;
reg [19:0] jump_base;
reg [19:0] jump_offset;
@ -175,7 +175,7 @@ initial
hex_dec = `MODE_HEX;
PC = 0;
new_PC = 0;
saved_PC = 0;
inst_start_PC = 0;
rstk_ptr = 7;
// $monitor("rst %b | CLK %b | CLK2 %b | CLK3 %b | PH0 %b | PH1 %b | PH2 %b | PH3 %b | CTR %d | EBCLK %b| STRB %b | BLPC %b | bnbi %b | bnbo %b | nb %b ",
@ -221,7 +221,6 @@ begin
cycle_ctr <= cycle_ctr + 1;
if (bus_load_pc) begin
bus_command <= `BUSCMD_LOAD_PC;
bus_address <= new_PC;
bus_load_pc <= 0;
en_bus_clk <= 1;
@ -242,7 +241,7 @@ begin
end
else begin
if (bus_command == `BUSCMD_LOAD_PC)
$display("CYCLE %d -> BUSCMD_LOAD_PC %h", cycle_ctr, PC);
$display("CYCLE %d -> BUSCMD_LOAD_PC %h", cycle_ctr, new_PC);
if (read_next_pc&read_nibble) begin
nibble <= bus_nibble_out;
en_dec_clk <= 1;
@ -303,7 +302,7 @@ always @(posedge dec_strobe) begin
$display("CYCLE %d | PC %h | DECSTATE %d | NIBBLE %h", cycle_ctr, PC, decstate, nibble);
case (decstate)
`DEC_START: begin
saved_PC <= PC;
inst_start_PC <= PC;
case (nibble)
4'h0: decstate <= `DEC_0X;
4'h2: decstate <= `DEC_P_EQ_N;