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implement more instructions, catch errors

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This commit is contained in:
Raphael Jacquot 2019-02-07 23:31:35 +01:00
parent 55bdfed19a
commit 24c49893a1
7 changed files with 148 additions and 126 deletions
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28
decstates.v
View file

@ -2,17 +2,21 @@
`define _DECSTATES
`define DEC_START 0 // X
`define DEC_P_EQ_N 1 // 2n
`define DEC_GOTO 2 // 6
`define DEC_GOTO_LOOP 3 // 6[x]
`define DEC_GOTO_EXEC 4 // 6xxx -> exec
`define DEC_8 5 // 8X
`define DEC_GOVLNG 6 // 8D
`define DEC_GOVLNG_LOOP 7 // 8D[x]
`define DEC_GOVLNG_EXEC 8 // 8Dxxxxx -> exec
`define DEC_GOSBVL 9 // 8F
`define DEC_GOSBVL_LOOP 10 // 8F[x]
`define DEC_GOSBVL_EXEC 11 // 8Fxxxxx -> exec
`define DEC_START 0 // X
`define DEC_P_EQ_N 1 // 2n
`define DEC_GOTO 2 // 6
`define DEC_GOTO_LOOP 3 // 6[x]
`define DEC_GOTO_EXEC 4 // 6xxx -> exec
`define DEC_8X 5 // 8X
`define DEC_80X 6 // 80X
`define DEC_C_EQ_P_N 7 // 80Cm
`define DEC_ST_EQ_0_N 8 // 84n
`define DEC_ST_EQ_1_N 9 // 85n
`define DEC_GOVLNG 10 // 8D
`define DEC_GOVLNG_LOOP 11 // 8D[x]
`define DEC_GOVLNG_EXEC 12 // 8Dxxxxx -> exec
`define DEC_GOSBVL 13 // 8F
`define DEC_GOSBVL_LOOP 14 // 8F[x]
`define DEC_GOSBVL_EXEC 15 // 8Fxxxxx -> exec
`endif

22
opcodes/80Cn_C_EQ_P_n.v
View file

@ -4,16 +4,12 @@
*
*/
DECODE_C_EQ_P_N:
begin
if (runstate == `RUN_DECODE)
runstate <= `INSTR_START;
if (runstate == `INSTR_READY)
begin
C[nibble*4+:4] <= P;
runstate <= `NEXT_INSTR;
`ifdef SIM
$display("%05h C=P\t%h", saved_PC, nibble);
`endif
end
end
`include "decstates.v"
`DEC_C_EQ_P_N: begin
C[nibble*4+:4] <= P;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h C=P\t%h", saved_PC, nibble);
`endif
end

68
opcodes/80x.v
View file

@ -5,31 +5,43 @@
*
*/
DECODE_80:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
`INSTR_READY:
begin
case (nibble)
4'h5: decstate <= DECODE_CONFIG;
4'ha: decstate <= DECODE_RESET;
4'hc: decstate <= DECODE_C_EQ_P_N;
default:
begin
`ifdef SIM
$display("unhandled instruction prefix 80%h", nibble);
`endif
decode_error <= 1;
end
endcase
runstate <= `RUN_DECODE;
end
default:
begin
`ifdef SIM
$display("DECODE_80: runstate %h", runstate);
`endif
decode_error <= 1;
end
endcase
`include "decstates.v"
`DEC_80X: begin
case (nibble)
4'hc: decstate <= `DEC_C_EQ_P_N;
default: begin
$display("ERROR : DEC_80X");
decode_error <= 1;
end
endcase
end
// DECODE_80:
// case (runstate)
// `RUN_DECODE: runstate <= `INSTR_START;
// `INSTR_START, `INSTR_STROBE: begin end
// `INSTR_READY:
// begin
// case (nibble)
// 4'h5: decstate <= DECODE_CONFIG;
// 4'ha: decstate <= DECODE_RESET;
// 4'hc: decstate <= DECODE_C_EQ_P_N;
// default:
// begin
// `ifdef SIM
// $display("unhandled instruction prefix 80%h", nibble);
// `endif
// decode_error <= 1;
// end
// endcase
// runstate <= `RUN_DECODE;
// end
// default:
// begin
// `ifdef SIM
// $display("DECODE_80: runstate %h", runstate);
// `endif
// decode_error <= 1;
// end
// endcase

41
opcodes/8[45]n_ST_EQ_[01]_n.v
View file

@ -3,28 +3,19 @@
* 85n ST=1 n
*/
DECODE_ST_EQ_0_N, DECODE_ST_EQ_1_N:
begin
if (runstate == `RUN_DECODE)
runstate <= `INSTR_START;
if (runstate == `INSTR_READY)
begin
case (decstate)
DECODE_ST_EQ_0_N:
begin
ST[nibble] <= 0;
`ifdef SIM
$display("%05h ST=0\t%h", saved_PC, nibble);
`endif
end
DECODE_ST_EQ_1_N:
begin
ST[nibble] <= 1;
`ifdef SIM
$display("%05h ST=1\t%h", saved_PC, nibble);
`endif
end
endcase
runstate <= `NEXT_INSTR;
end
end
`include "decstates.v"
`DEC_ST_EQ_0_N: begin
ST[nibble] <= 0;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h ST=0\t%h", saved_PC, nibble);
`endif
end
`DEC_ST_EQ_1_N: begin
ST[nibble] <= 1;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h ST=1\t%h", saved_PC, nibble);
`endif
end

10
opcodes/8x.v
View file

@ -7,11 +7,17 @@
`include "decstates.v"
`DEC_8: begin
`DEC_8X: begin
case (nibble)
4'h0: decstate <= `DEC_80X;
4'h4: decstate <= `DEC_ST_EQ_0_N;
4'h5: decstate <= `DEC_ST_EQ_1_N;
4'hD: decstate <= `DEC_GOVLNG;
4'hF: decstate <= `DEC_GOSBVL;
default: begin end
default: begin
$display("ERROR : DEC_8X");
decode_error <= 1;
end
endcase
end

83
saturn_core.json
View file

@ -14327,7 +14327,7 @@
}
},
"cells": {
"$abc$771$auto$blifparse.cc:492:parse_blif$772": {
"$abc$2094$auto$blifparse.cc:492:parse_blif$2095": {
"hide_name": 1,
"type": "LUT4",
"parameters": {
@ -14352,7 +14352,7 @@
"Z": [ 22 ]
}
},
"$auto$alumacc.cc:474:replace_alu$625.slice[0].ccu2c_i": {
"$auto$alumacc.cc:474:replace_alu$1931.slice[0].ccu2c_i": {
"hide_name": 1,
"type": "CCU2C",
"parameters": {
@ -14363,7 +14363,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:282|/usr/local/bin/../share/yosys/ecp5/arith_map.v:58"
"src": "saturn_core.v:324|/usr/local/bin/../share/yosys/ecp5/arith_map.v:58"
},
"port_directions": {
"A0": "input",
@ -14394,7 +14394,7 @@
"S1": [ 25 ]
}
},
"$auto$alumacc.cc:474:replace_alu$625.slice[2].ccu2c_i": {
"$auto$alumacc.cc:474:replace_alu$1931.slice[2].ccu2c_i": {
"hide_name": 1,
"type": "CCU2C",
"parameters": {
@ -14405,7 +14405,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:282|/usr/local/bin/../share/yosys/ecp5/arith_map.v:58"
"src": "saturn_core.v:324|/usr/local/bin/../share/yosys/ecp5/arith_map.v:58"
},
"port_directions": {
"A0": "input",
@ -14436,7 +14436,7 @@
"S1": [ 28 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$696": {
"$auto$simplemap.cc:420:simplemap_dff$2031": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14449,7 +14449,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
},
"port_directions": {
"CLK": "input",
@ -14464,7 +14464,7 @@
"Q": [ 10 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$697": {
"$auto$simplemap.cc:420:simplemap_dff$2032": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14477,7 +14477,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
},
"port_directions": {
"CLK": "input",
@ -14492,7 +14492,7 @@
"Q": [ 11 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$698": {
"$auto$simplemap.cc:420:simplemap_dff$2033": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14505,7 +14505,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
},
"port_directions": {
"CLK": "input",
@ -14520,7 +14520,7 @@
"Q": [ 12 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$699": {
"$auto$simplemap.cc:420:simplemap_dff$2034": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14533,7 +14533,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
},
"port_directions": {
"CLK": "input",
@ -14548,7 +14548,7 @@
"Q": [ 13 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$700": {
"$auto$simplemap.cc:420:simplemap_dff$2035": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14561,7 +14561,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
},
"port_directions": {
"CLK": "input",
@ -14576,7 +14576,7 @@
"Q": [ 14 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$701": {
"$auto$simplemap.cc:420:simplemap_dff$2036": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14589,7 +14589,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
},
"port_directions": {
"CLK": "input",
@ -14604,7 +14604,7 @@
"Q": [ 15 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$702": {
"$auto$simplemap.cc:420:simplemap_dff$2037": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14617,7 +14617,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
},
"port_directions": {
"CLK": "input",
@ -14632,7 +14632,7 @@
"Q": [ 16 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$703": {
"$auto$simplemap.cc:420:simplemap_dff$2038": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14645,7 +14645,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
},
"port_directions": {
"CLK": "input",
@ -14660,7 +14660,7 @@
"Q": [ 17 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$704": {
"$auto$simplemap.cc:420:simplemap_dff$2039": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14673,7 +14673,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
},
"port_directions": {
"CLK": "input",
@ -14688,7 +14688,7 @@
"Q": [ 18 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$705": {
"$auto$simplemap.cc:420:simplemap_dff$2040": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14701,7 +14701,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
},
"port_directions": {
"CLK": "input",
@ -14716,7 +14716,7 @@
"Q": [ 19 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$706": {
"$auto$simplemap.cc:420:simplemap_dff$2041": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14729,7 +14729,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
},
"port_directions": {
"CLK": "input",
@ -14744,7 +14744,7 @@
"Q": [ 20 ]
}
},
"$auto$simplemap.cc:420:simplemap_dff$707": {
"$auto$simplemap.cc:420:simplemap_dff$2042": {
"hide_name": 1,
"type": "TRELLIS_FF",
"parameters": {
@ -14757,7 +14757,7 @@
},
"attributes": {
"module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
"src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
},
"port_directions": {
"CLK": "input",
@ -14774,30 +14774,31 @@
}
},
"netnames": {
"$abc$771$n2": {
"$abc$2094$n2": {
"hide_name": 1,
"bits": [ 22 ],
"attributes": {
}
},
"$add$saturn_core.v:282$379_Y": {
"$add$saturn_core.v:324$398_Y": {
"hide_name": 1,
"bits": [ 24, 25, 27, 28 ],
"bits": [ 24, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 ],
"attributes": {
"src": "saturn_core.v:324"
}
},
"$auto$alumacc.cc:474:replace_alu$625.C": {
"$auto$alumacc.cc:474:replace_alu$1931.C": {
"hide_name": 1,
"bits": [ 29, 30, 23, 31 ],
"bits": [ 57, 58, 23, 59 ],
"attributes": {
"src": "saturn_core.v:282|/usr/local/bin/../share/yosys/ecp5/arith_map.v:53"
"src": "saturn_core.v:324|/usr/local/bin/../share/yosys/ecp5/arith_map.v:53"
}
},
"$auto$alumacc.cc:474:replace_alu$625.FCO": {
"$auto$alumacc.cc:474:replace_alu$1931.FCO": {
"hide_name": 1,
"bits": [ 32, 33, 26, 34 ],
"bits": [ 60, 61, 26, 62 ],
"attributes": {
"src": "saturn_core.v:282|/usr/local/bin/../share/yosys/ecp5/arith_map.v:54",
"src": "saturn_core.v:324|/usr/local/bin/../share/yosys/ecp5/arith_map.v:54",
"unused_bits": "0 1 2 3"
}
},
@ -14812,14 +14813,14 @@
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "saturn_core.v:143|hp48_bus.v:38|hp48_io_ram.v:17"
"src": "saturn_core.v:145|hp48_bus.v:38|hp48_io_ram.v:17"
}
},
"bus_ctrl.reset": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "saturn_core.v:143|hp48_bus.v:19"
"src": "saturn_core.v:145|hp48_bus.v:19"
}
},
"clk": {
@ -14847,7 +14848,7 @@
"hide_name": 0,
"bits": [ 18, 19, 20, 21 ],
"attributes": {
"src": "saturn_core.v:90"
"src": "saturn_core.v:92"
}
},
"reset": {

22
saturn_core.v
View file

@ -81,6 +81,7 @@ wire dec_strobe;
wire halt;
reg [31:0] cycle_ctr;
reg decode_error;
reg debug_stop;
reg [3:0] busstate;
reg read_next_pc;
@ -168,6 +169,7 @@ initial
decstate = 0;
$display("initializing control bits");
decode_error = 0;
debug_stop = 0;
bus_load_pc = 1;
read_next_pc = 1;
execute_cycle = 0;
@ -258,8 +260,8 @@ always @(posedge ph2)
end
always @(posedge ph3) begin
if (cycle_ctr == 20)
decode_error <= 1;
if (cycle_ctr == 48)
debug_stop <= 1;
end
//--------------------------------------------------------------------------------------------------
@ -292,14 +294,24 @@ always @(posedge dec_strobe) begin
case (nibble)
4'h2: decstate <= `DEC_P_EQ_N;
4'h6: decstate <= `DEC_GOTO;
4'h8: decstate <= `DEC_8;
default: begin end
4'h8: decstate <= `DEC_8X;
default: begin
$display("ERROR : DEC_START");
decode_error <= 1;
end
endcase
end
`include "opcodes/2n_P_EQ_n.v"
`include "opcodes/6xxx_GOTO.v"
`include "opcodes/8x.v"
`include "opcodes/80x.v"
`include "opcodes/80Cn_C_EQ_P_n.v"
`include "opcodes/8[45]n_ST_EQ_[01]_n.v"
`include "opcodes/8[DF]xxxxx_GO.v"
default: begin
$display("ERROR : GENERAL");
decode_error <= 1;
end
endcase
end
@ -327,7 +339,7 @@ begin
end
`endif
assign halt = bus_error | decode_error;
assign halt = bus_error | decode_error | debug_stop;
// Verilator lint_off UNUSED