mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-31 19:57:50 +01:00
finish re-coding all instructions
This commit is contained in:
Raphael Jacquot
parent
40d75acc8f
commit
14272d9978
3 changed files with 31692 additions and 322934 deletions
2
compile
2
compile
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@ -2,4 +2,4 @@
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#yosys -p "synth_ecp5 -top mask_gen -json mask_gen.json" mask_gen.v
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#nextpnr-ecp5 --gui --um-85k --speed 6 --freq 5 --json mask_gen.json --save mask_gen.ecp5
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yosys -p "synth_ecp5 -top saturn_core -json saturn_core.json" saturn_core.v
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nextpnr-ecp5 --gui --um-85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5
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nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5
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354230
saturn_core.json
354230
saturn_core.json
File diff suppressed because it is too large
Load diff
394
saturn_core.v
394
saturn_core.v
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@ -49,7 +49,7 @@ module saturn_core (
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input reset,
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output halt,
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output [3:0] runstate,
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output [31:0] decstate
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output [15:0] decstate
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);
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`else
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module saturn_core (
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@ -68,7 +68,7 @@ assign reset = btn[1];
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`endif
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// led display states
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localparam REGDMP_HEX = 16'h0000;
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localparam REGDMP_HEX = 8'h00;
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// runstate
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@ -83,48 +83,48 @@ localparam RUN_DECODE = 15;
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// instruction decoder states
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localparam DECODE_START = 32'h00000000;
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localparam DECODE_START = 16'h0000;
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localparam DECODE_0 = 32'h00000001;
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localparam DECODE_0X = 32'h00000002;
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localparam DECODE_0 = 16'h0001;
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localparam DECODE_0X = 16'h0002;
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localparam DECODE_RTNCC = 32'h00000300;
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localparam DECODE_SETHEX = 32'h00000400;
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localparam DECODE_SETDEC = 32'h00000500;
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localparam DECODE_RTNCC = 16'h0300;
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localparam DECODE_SETHEX = 16'h0400;
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localparam DECODE_SETDEC = 16'h0500;
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localparam DECODE_1 = 32'h00000010;
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localparam DECODE_1X = 32'h00000011;
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localparam DECODE_14 = 32'h00000410;
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localparam DECODE_15 = 32'h00000510;
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localparam DECODE_MEMACCESS = 32'h00000411;
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localparam DECODE_D0_EQ_5N = 32'h00000b10;
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localparam DECODE_1 = 16'h0010;
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localparam DECODE_1X = 16'h0011;
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localparam DECODE_14 = 16'h0410;
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localparam DECODE_15 = 16'h0510;
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localparam DECODE_MEMACCESS = 16'h0411;
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localparam DECODE_D0_EQ_5N = 16'h0b10;
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localparam DECODE_P_EQ = 32'h00000020;
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localparam DECODE_P_EQ = 16'h0020;
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localparam DECODE_LC_LEN = 32'h00000030;
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localparam DECODE_LC = 32'h00000031;
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localparam DECODE_LC_LEN = 16'h0030;
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localparam DECODE_LC = 16'h0031;
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localparam DECODE_GOTO = 32'h00000060;
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localparam DECODE_GOTO = 16'h0060;
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localparam DECODE_8 = 32'h00000080;
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localparam DECODE_8X = 32'h00000081;
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localparam DECODE_80 = 32'h00000082;
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localparam DECODE_8 = 16'h0080;
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localparam DECODE_8X = 16'h0081;
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localparam DECODE_80 = 16'h0082;
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localparam DECODE_CONFIG = 32'h00005080;
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localparam DECODE_RESET = 32'h0000A080;
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localparam DECODE_CONFIG = 16'h5080;
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localparam DECODE_RESET = 16'hA080;
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localparam DECODE_C_EQ_P_N = 32'h0000C080;
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localparam DECODE_C_EQ_P_N = 16'hC080;
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localparam DECODE_82 = 32'h00000280;
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localparam DECODE_82 = 16'h0280;
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localparam DECODE_ST_EQ_0_N = 32'h00000480;
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localparam DECODE_ST_EQ_1_N = 32'h00000580;
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localparam DECODE_ST_EQ_0_N = 16'h0480;
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localparam DECODE_ST_EQ_1_N = 16'h0580;
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localparam DECODE_GOVLNG = 32'h00000d80;
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localparam DECODE_GOSBVL = 32'h00000f80;
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localparam DECODE_GOVLNG = 16'h0d80;
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localparam DECODE_GOSBVL = 16'h0f80;
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localparam DECODE_A = 32'h000000a0;
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localparam DECODE_A_FS = 32'h000000a1;
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localparam DECODE_A = 16'h00a0;
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localparam DECODE_A_FS = 16'h00a1;
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localparam HEX = 0;
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localparam DEC = 1;
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@ -132,8 +132,8 @@ localparam DEC = 1;
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// state machine stuff
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reg halt;
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reg [3:0] runstate;
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reg [31:0] decstate;
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reg [15:0] regdump;
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reg [15:0] decstate;
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reg [7:0] regdump;
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// memory access
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//reg rom_clock;
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@ -303,13 +303,13 @@ begin
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runstate <= RUN_DECODE;
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case (nibble)
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4'h0 : decstate <= DECODE_0;
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//4'h1 : decstate <= DECODE_1;
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4'h1 : decstate <= DECODE_1;
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4'h2 : decstate <= DECODE_P_EQ;
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4'h3 : decstate <= DECODE_LC_LEN;
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4'h6 : decstate <= DECODE_GOTO;
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4'h8 : decstate <= DECODE_8;
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//4'ha : decstate <= DECODE_A_FS;
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4'ha : decstate <= DECODE_A;
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default:
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begin
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`ifdef SIM
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@ -320,6 +320,12 @@ begin
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endcase
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end
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/******************************************************************************
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* 0X
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*
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*
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*/
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if (decstate == DECODE_0)
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case (runstate)
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RUN_DECODE: runstate <= READ_ROM_STA;
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@ -347,8 +353,6 @@ begin
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end
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endcase
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/******************************************************************************
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* 03 RTNCC
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*
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@ -368,21 +372,6 @@ begin
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decstate <= DECODE_START;
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end
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/*
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// 03 RTNCC
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task inst_rtncc;
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begin
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Carry = 0;
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PC = RSTK[rstk_ptr];
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RSTK[rstk_ptr] = 0;
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rstk_ptr = rstk_ptr - 1;
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$display("%05h RTNCC", saved_PC);
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end_decode();
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end
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endtask
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*/
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/******************************************************************************
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* 04 SETHEX
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*
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@ -415,85 +404,132 @@ endtask
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decstate <= DECODE_START;
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end
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/******************************************************************************
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* 1X
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*
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*
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*/
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if (decstate == DECODE_1)
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case (runstate)
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RUN_DECODE: runstate <= READ_ROM_STA;
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READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: begin end
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READ_ROM_VAL:
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begin
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case (nibble)
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//4'h4, 4'h5: decode_14_15();
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4'h4: decstate <= DECODE_14;
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4'hb: decstate <= DECODE_D0_EQ_5N;
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default:
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begin
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`ifdef SIM
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$display("unhandled instruction prefix 1%h", nibble);
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`endif
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halt <= 1;
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end
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endcase
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runstate <= RUN_DECODE;
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end
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default:
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begin
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`ifdef SIM
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$display("decstate %h", decstate);
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`endif
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halt <= 1;
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end
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endcase
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/*
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task decode_1;
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case (decstate )
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DECODE_START:
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begin
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decstate = DECODE_1X;
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read_state = READ_START;
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end
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DECODE_1X:
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if (read_state != READ_VALID) read_rom();
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else decode_1x();
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endcase
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endtask
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/******************************************************************************
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* 1[45]
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*
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* ---------- field -----------
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* A B fs d
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* ----------------------------
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* 140 148 150a 158x DAT0=A field
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* 141 149 151a 159x DAT1=A field
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* 142 14A 152a 15Ax A=DAT0 field
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* 143 14B 153a 15Bx A=DAT1 field
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* 144 14C 154a 15Cx DAT0=C field
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* 145 14D 155a 15Dx DAT1=C field
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* 146 14E 156a 15Ex C=DAT0 field
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* 147 14F 157a 15Fx C=DAT1 field
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*
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* fs: P WP XS X S M B W
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* a: 0 1 2 3 4 5 6 7
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*
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* x = d - 1 x = n - 1
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*
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*/
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task decode_1x;
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case (nibble)
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4'h4, 4'h5: decode_14_15();
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4'hb: inst_d0_eq_5n();
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default: instruction_decoder_unhandled();
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endcase
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endtask
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task decode_14_15;
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case (decstate)
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DECODE_1X:
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begin
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read_state <= READ_START;
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case (nibble)
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4'h4: decstate <= DECODE_14;
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4'h5: decstate <= DECODE_15;
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endcase
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end
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DECODE_14, DECODE_15:
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if (read_state != READ_VALID) read_rom();
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else
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if ((decstate == DECODE_14)|(decstate == DECODE_15))
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case (runstate)
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RUN_DECODE: runstate <= READ_ROM_STA;
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READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: begin end
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READ_ROM_VAL:
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case (nibble)
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default:
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begin
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$display("memacess %h %h", decstate[11:8], nibble);
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halt_processor();
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`ifdef SIM
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$display("runstate %h %h", decstate, nibble);
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`endif
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halt <= 1;
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end
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endcase
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endcase
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endtask
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// 1bnnnnn DO=(5) nnnnn
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task inst_d0_eq_5n;
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case (decstate )
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DECODE_1X:
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begin
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decstate = DECODE_D0_EQ_5N;
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read_state = READ_START;
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load_cnt = 4;
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load_ctr = 0;
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$write("%5h D0=(5)\t", saved_PC);
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end
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DECODE_D0_EQ_5N:
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if (read_state != READ_VALID) read_rom();
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else
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default:
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begin
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D0[load_ctr*4+:4] = nibble;
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`ifdef SIM
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$display("runstate %h", decstate);
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`endif
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halt <= 1;
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end
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endcase
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/******************************************************************************
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*1bnnnnn DO=(5) nnnnn
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*
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*
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*/
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if (decstate == DECODE_D0_EQ_5N)
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case (runstate)
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RUN_DECODE:
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begin
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runstate <= READ_ROM_STA;
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load_cnt <= 4;
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load_ctr <= 0;
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`ifdef SIM
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$write("%5h D0=(5)\t", saved_PC);
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`endif
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end
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READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: begin end
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READ_ROM_VAL:
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begin
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D0[load_ctr*4+:4] <= nibble;
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`ifdef SIM
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$write("%1h", nibble);
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if (load_ctr == load_cnt)
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`endif
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if (load_ctr == load_cnt)
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begin
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`ifdef SIM
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$display("");
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end_decode();
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end
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`endif
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runstate <= RUN_START;
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decstate <= DECODE_START;
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end
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else
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begin
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load_ctr = load_ctr + 1;
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read_state = READ_START;
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load_ctr <= load_ctr + 1;
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runstate <= READ_ROM_STA;
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end
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end
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endcase
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endtask
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*/
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default:
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begin
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`ifdef SIM
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$display("runstate %h", runstate);
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`endif
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halt <= 1;
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end
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endcase
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/******************************************************************************
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* 2n P= n
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@ -563,7 +599,7 @@ endtask
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end
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else
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begin
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load_ctr <= (load_ctr + 1)%4'hf;
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load_ctr <= (load_ctr + 1)&4'hf;
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runstate <= READ_ROM_STA;
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end
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end
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@ -901,71 +937,65 @@ endtask
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end
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endcase
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/*
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task decode_a;
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case (decstate)
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DECODE_START:
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begin
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decstate <= DECODE_A;
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read_state <= READ_START;
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end
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DECODE_A:
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if (read_state != READ_VALID) read_rom();
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else
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begin
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tmp_field <= nibble;
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decstate <= DECODE_A_FS;
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read_state <= READ_START;
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end
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endcase
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endtask
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task decode_a_fs;
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case (decstate)
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DECODE_A_FS:
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if (read_state != READ_VALID) read_rom();
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else
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begin
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$write("%5h ", saved_PC);
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case (tmp_field)
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4'h0, 4'h1, 4'h2, 4'h3, 4'h4, 4'h5, 4'h6, 4'h7:
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begin
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$display("a%h%h", tmp_field, nibble);
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halt_processor();
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end
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4'h8, 4'h9, 4'ha, 4'hb, 4'hc, 4'hd, 4'he, 4'hf:
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begin
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case (nibble)
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4'h2: // C=0 fs
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begin
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$write("C=0\t");
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case (tmp_field)
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4'he: C[7:0] <= 0;
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default:
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begin
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$display("a%h%h", tmp_field, nibble);
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halt_processor();
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end
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endcase
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end
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default:
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begin
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$display("a%h%h", tmp_field, nibble);
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halt_processor();
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end
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endcase
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case (tmp_field)
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4'he: $display("B");
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endcase
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if (~halt)
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end_decode();
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end
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endcase
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end
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endcase
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endtask
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*/
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/******************************************************************************
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* A[ab]x
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*
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* lots of things there
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*
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*/
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if ((decstate == DECODE_A)|(decstate == DECODE_A_FS))
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case (runstate)
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RUN_DECODE: runstate <= READ_ROM_STA;
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READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: begin end
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READ_ROM_VAL:
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case (decstate)
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DECODE_A:
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begin
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tmp_field <= nibble;
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decstate <= DECODE_A_FS;
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runstate <= READ_ROM_STA;
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end
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DECODE_A_FS:
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begin
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case (nibble)
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4'h2:
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case (tmp_field)
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4'he:
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begin
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C[7:0] <= 0;
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`ifdef SIM
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$display("%5h C=0\tB", saved_PC);
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`endif
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end
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endcase
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default:
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begin
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`ifdef SIM
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$display("decstate %h %h %h", decstate, tmp_field, nibble);
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`endif
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halt <= 1;
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end
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endcase
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runstate <= RUN_START;
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decstate <= DECODE_START;
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end
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default:
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begin
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`ifdef SIM
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$display("decstate %h %h", decstate, nibble);
|
||||
`endif
|
||||
halt <= 1;
|
||||
end
|
||||
endcase
|
||||
default:
|
||||
begin
|
||||
`ifdef SIM
|
||||
$display("decstate %h", decstate);
|
||||
`endif
|
||||
halt <= 1;
|
||||
end
|
||||
endcase
|
||||
|
||||
/**************************************************************************************************
|
||||
*
|
||||
|
|
@ -973,6 +1003,7 @@ endtask
|
|||
*
|
||||
*/
|
||||
|
||||
`ifndef SIM
|
||||
|
||||
case (regdump)
|
||||
REGDMP_HEX: led <= {7'b0000000, hex_dec};
|
||||
|
|
@ -980,6 +1011,7 @@ endtask
|
|||
endcase
|
||||
regdump <= regdump + 1;
|
||||
|
||||
`endif
|
||||
|
||||
end
|
||||
// Verilator lint_off UNUSED
|
||||
|
|
@ -995,7 +1027,7 @@ reg clk;
|
|||
reg reset;
|
||||
wire halt;
|
||||
wire [3:0] runstate;
|
||||
wire [31:0] decstate;
|
||||
wire [15:0] decstate;
|
||||
|
||||
saturn_core saturn (
|
||||
.clk (clk),
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue