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https://github.com/sxpert/hp-saturn
synced 2025-01-19 10:26:58 +01:00
implement some of the bus commands for the io_ram module.
This commit is contained in:
Raphael Jacquot
parent
82f4df8e93
commit
c77b714777
2 changed files with 35744 additions and 29851 deletions
65395
saturn_core.json
65395
saturn_core.json
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200
saturn_core.v
200
saturn_core.v
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@ -49,15 +49,19 @@ endmodule
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*/
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`define BUSCMD_NOP 0
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`define BUSCMD_DP_WRITE 5
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`define BUSCMD_LOAD_DP 7
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`define BUSCMD_CONFIGURE 8
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module hp48_io_ram (
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input clk,
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input reset,
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input [19:0] address,
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input [3:0] command,
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input [3:0] nibble_in,
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output [3:0] nibble_out
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output [3:0] nibble_out,
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output reg io_ram_active,
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output reg io_ram_error
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);
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localparam IO_RAM_LEN = 64;
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@ -66,16 +70,34 @@ localparam IO_RAM_LEN = 64;
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// localparam BUSCMD_CONFIGURE = C_BUSCMD_CONFIGURE;
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reg configured;
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reg [0:0] configured;
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reg [19:0] base_addr;
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reg [19:0] data_ptr;
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reg [3:0] io_ram [0:IO_RAM_LEN-1];
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/*
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*
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*
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*/
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initial
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begin
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`ifdef SIM
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$display("io_ram: unconfigured");
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$display("io_ram: set unconfigured");
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`endif
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configured = 0;
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`ifdef SIM
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$display("io_ram: reset error flag");
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`endif
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io_ram_error = 0;
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`ifdef SIM
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$display("io_ram: setting base address to 0");
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`endif
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base_addr = 0;
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`ifdef SIM
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$display("io_ram: setting data pointer to 0");
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`endif
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data_ptr = 0;
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`ifdef SIM
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$display("io_ram: initializing to 0");
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`endif
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@ -88,28 +110,69 @@ initial
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end
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`ifdef SIM
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$display("");
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$display("io_ram: setting base address to 0");
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`endif
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base_addr = 0;
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`ifdef SIM
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$display("io_ram: initialized");
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`endif
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end
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always @(posedge clk)
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/*
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*
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*
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*/
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always @(*)
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case (command)
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`BUSCMD_NOP: begin end // do nothing
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`BUSCMD_CONFIGURE:
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begin
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`ifdef SIM
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$display("io_ram: configure at %5h len %d", address, IO_RAM_LEN);
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`endif
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base_addr <= address;
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end
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default:
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$display("io_ram: unhandled command %h", command);
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`BUSCMD_DP_WRITE:
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io_ram_active = ((base_addr >= data_ptr)&(data_ptr < base_addr+IO_RAM_LEN))&(configured);
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endcase
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always @(negedge clk)
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if ((~reset)&(~io_ram_error))
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case (command)
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`BUSCMD_NOP: begin end // do nothing
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`BUSCMD_DP_WRITE:
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begin
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`ifdef SIM
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$write("io_ram: DP_WRITE %5h %h | ", data_ptr, nibble_in);
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`endif
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// test if write can be done
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if (io_ram_active)
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begin
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io_ram[data_ptr - base_addr] <= nibble_in;
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data_ptr <= data_ptr + 1;
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`ifdef SIM
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$display("OK");
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`endif
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end
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else
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`ifdef SIM
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$display("NOK - IO_RAM not active (conf: %b)", configured);
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`endif
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end
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`BUSCMD_LOAD_DP:
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begin
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`ifdef SIM
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$display("io_ram: LOAD_DP %5h", address);
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`endif
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data_ptr <= address;
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end
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`BUSCMD_CONFIGURE:
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begin
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`ifdef SIM
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$display("io_ram: configure at %5h len %d", address, IO_RAM_LEN);
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`endif
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base_addr <= address;
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configured <= 1;
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end
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default:
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begin
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`ifdef SIM
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$display("io_ram: unhandled command %h", command);
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`endif
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io_ram_error <= 1;
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end
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endcase
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endmodule
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@ -163,6 +226,7 @@ localparam READ_ROM_CLK = 2;
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localparam READ_ROM_STR = 3;
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localparam READ_ROM_VAL = 4;
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localparam WRITE_STA = 5;
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localparam WRITE_STROBE = 6;
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localparam WRITE_DONE = 8;
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localparam RUN_EXEC = 14;
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localparam RUN_DECODE = 15;
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@ -237,21 +301,20 @@ localparam T_FIELD_LEN = 13;
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localparam T_FIELD_A = 15;
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// state machine stuff
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reg halt;
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reg [3:0] runstate;
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reg [15:0] decstate;
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reg [7:0] regdump;
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reg halt;
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reg [3:0] runstate;
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reg [15:0] decstate;
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reg [7:0] regdump;
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// memory access
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//reg rom_clock;
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reg [19:0] rom_address;
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reg rom_enable;
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wire[3:0] rom_nibble;
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// io_ram access
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// bus access
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reg [19:0] bus_address;
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reg [3:0] bus_command;
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reg [3:0] nibble_in;
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wire [3:0] nibble_out;
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wire io_ram_error;
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// should go away, the rom should work like any other bus module
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reg rom_enable;
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// internal registers
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reg [3:0] nibble;
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@ -293,17 +356,19 @@ reg [63:0] R4;
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hp_rom calc_rom (
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.clk (clk),
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.address (rom_address),
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.address (bus_address),
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.enable (rom_enable),
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.nibble_out (rom_nibble)
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.nibble_out (nibble_out)
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);
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hp48_io_ram io_ram (
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.clk (clk),
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.address (rom_address),
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.command (bus_command),
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.nibble_in (nibble_in),
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.nibble_out (nibble_out)
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.clk (clk),
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.reset (reset),
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.address (bus_address),
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.command (bus_command),
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.nibble_in (nibble_in),
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.nibble_out (nibble_out),
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.io_ram_error (io_ram_error)
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);
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/**************************************************************************************************
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*
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@ -366,6 +431,11 @@ begin
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if (runstate == RUN_START)
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runstate <= READ_ROM_STA;
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if (io_ram_error)
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begin
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halt <= 1;
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end
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//--------------------------------------------------------------------------------------------------
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//
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// REGISTER UTILITIES
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@ -399,7 +469,7 @@ begin
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begin
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//$display("READ_ROM_STA");
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rom_enable <= 1'b1;
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rom_address <= PC;
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bus_address <= PC;
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runstate <= READ_ROM_CLK;
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end
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@ -415,8 +485,8 @@ begin
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if (runstate == READ_ROM_STR)
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begin
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//$display("READ_ROM_STR");
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nibble <= rom_nibble;
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//$display("PC: %h | read => %h", PC, rom_nibble);
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nibble <= nibble_out;
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//$display("PC: %h | read => %h", PC, nibble_out);
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PC <= PC + 1;
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rom_enable <= 1'b0;
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// rom_clock <= 1'b0;
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@ -583,14 +653,14 @@ begin
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* ---------- field -----------
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* A B fs d
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* ----------------------------
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* 140 148 150a 158x DAT0=A field
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* 141 149 151a 159x DAT1=A field
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* 142 14A 152a 15Ax A=DAT0 field
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* 143 14B 153a 15Bx A=DAT1 field
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* 144 14C 154a 15Cx DAT0=C field
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* 145 14D 155a 15Dx DAT1=C field
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* 146 14E 156a 15Ex C=DAT0 field
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* 147 14F 157a 15Fx C=DAT1 field
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* 140 148 150a 158x DAT0=A field 0000 1000
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* 141 149 151a 159x DAT1=A field 0001 1001
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* 142 14A 152a 15Ax A=DAT0 field 0010 1010
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* 143 14B 153a 15Bx A=DAT1 field 0011 1011
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* 144 14C 154a 15Cx DAT0=C field 0100 1100
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* 145 14D 155a 15Dx DAT1=C field 0101 1101
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* 146 14E 156a 15Ex C=DAT0 field 0110 1110
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* 147 14F 157a 15Fx C=DAT1 field 0111 1111
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*
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* fs: P WP XS X S M B W
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* a: 0 1 2 3 4 5 6 7
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@ -671,7 +741,41 @@ begin
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endcase
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`endif
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end
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WRITE_STA:
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begin
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`ifdef SIM
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$display("WRITE_STA | ptr %s | dir %s | reg %s | field %h | off %h | ctr %h | cnt %h",
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t_ptr?"D1":"D0", t_dir?"IN":"OUT", t_reg?"C":"A", t_field, t_field, t_offset, t_ctr, t_cnt);
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`endif
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bus_command <= `BUSCMD_LOAD_DP;
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bus_address <= (~t_ptr)?D0:D1;
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runstate <= WRITE_STROBE;
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end
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WRITE_STROBE:
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begin
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`ifdef SIM
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$display("WRITE_STROBE | ptr %s | dir %s | reg %s | field %h | off %h | ctr %h | cnt %h",
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t_ptr?"D1":"D0", t_dir?"IN":"OUT", t_reg?"C":"A", t_field, t_offset, t_ctr, t_cnt);
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`endif
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bus_command <= `BUSCMD_DP_WRITE;
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nibble_in <= (~t_reg)?A[t_offset*4+:4]:C[t_offset*4+:4];
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t_offset <= t_offset + 1;
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t_ctr <= t_ctr + 1;
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if (t_ctr == t_cnt)
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begin
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runstate <= WRITE_DONE;
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end
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end
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WRITE_DONE:
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begin
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`ifdef SIM
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$display("WRITE_DONE | ptr %s | dir %s | reg %s | field %h | off %h | ctr %h | cnt %h",
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t_ptr?"D1":"D0", t_dir?"IN":"OUT", t_reg?"C":"A", t_field, t_offset, t_ctr, t_cnt);
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`endif
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bus_command <= `BUSCMD_NOP;
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runstate <= RUN_START;
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decstate <= DECODE_START;
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end
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default:
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begin
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`ifdef SIM
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