mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-26 09:58:09 +01:00
569 lines
22 KiB
Verilog
569 lines
22 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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`include "saturn_def_debugger.v"
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`include "saturn_def_alu.v"
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module saturn_debugger (
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i_clk,
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i_clk_en,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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o_debug_cycle,
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/* interface from the control unit */
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i_current_pc,
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i_reg_alu_mode,
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i_reg_hst,
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i_reg_st,
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i_reg_p,
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o_dbg_register,
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o_dbg_reg_ptr,
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i_dbg_reg_nibble,
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o_dbg_rstk_ptr,
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i_dbg_rstk_val,
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i_reg_rstk_ptr,
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i_alu_reg_dest,
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i_alu_reg_src_1,
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i_alu_reg_src_2,
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i_alu_imm_value,
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i_alu_opcode,
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i_instr_type,
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i_instr_decoded,
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/* output to leds */
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o_char_to_send,
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o_char_counter,
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o_char_valid,
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o_char_send,
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i_serial_busy,
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i_bus_nibble_in,
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i_bus_read_valid
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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output reg [0:0] o_debug_cycle;
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/* inteface from the control unit */
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input wire [19:0] i_current_pc;
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input wire [0:0] i_reg_alu_mode;
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input wire [3:0] i_reg_hst;
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input wire [15:0] i_reg_st;
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input wire [3:0] i_reg_p;
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output reg [4:0] o_dbg_register;
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output wire [3:0] o_dbg_reg_ptr;
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assign o_dbg_reg_ptr = registers_reg_ptr[3:0];
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input wire [3:0] i_dbg_reg_nibble;
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output reg [2:0] o_dbg_rstk_ptr;
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input wire [19:0] i_dbg_rstk_val;
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input wire [2:0] i_reg_rstk_ptr;
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input wire [4:0] i_alu_reg_dest;
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input wire [4:0] i_alu_reg_src_1;
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input wire [4:0] i_alu_reg_src_2;
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input wire [3:0] i_alu_imm_value;
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input wire [4:0] i_alu_opcode;
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input wire [3:0] i_instr_type;
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input wire [0:0] i_instr_decoded;
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output reg [7:0] o_char_to_send;
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output wire [9:0] o_char_counter;
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assign o_char_counter = {1'b0, counter};
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output reg [0:0] o_char_valid;
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output reg [0:0] o_char_send;
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input wire [0:0] i_serial_busy;
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input wire [3:0] i_bus_nibble_in;
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input wire [0:0] i_bus_read_valid;
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/**************************************************************************************************
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*
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* debugger process registers
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*
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*************************************************************************************************/
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reg [8:0] counter;
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reg [0:0] write_out;
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wire [0:0] debug_done;
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assign debug_done = registers_done;
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reg [7:0] hex[0:15];
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reg [8:0] registers_ctr;
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reg [7:0] registers_str[0:511];
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reg [6:0] registers_state;
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reg [5:0] registers_reg_ptr;
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reg [0:0] registers_done;
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reg [0:0] carry;
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initial begin
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o_debug_cycle = 1'b0;
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counter = 9'd0;
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write_out = 1'b0;
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hex[0] = "0";
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hex[1] = "1";
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hex[2] = "2";
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hex[3] = "3";
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hex[4] = "4";
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hex[5] = "5";
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hex[6] = "6";
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hex[7] = "7";
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hex[8] = "8";
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hex[9] = "9";
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hex[10] = "A";
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hex[11] = "B";
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hex[12] = "C";
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hex[13] = "D";
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hex[14] = "E";
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hex[15] = "F";
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registers_ctr = 9'd0;
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registers_state = `DBG_REG_PC_STR;
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registers_reg_ptr = 6'b0;
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o_dbg_register = `ALU_REG_NONE;
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registers_done = 1'b0;
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o_char_valid = 1'b0;
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o_char_send = 1'b0;
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carry = 1'b1;
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end
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/**************************************************************************************************
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*
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* debugger process
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*
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*************************************************************************************************/
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always @(posedge i_clk) begin
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if (i_clk_en && i_phases[3] && i_instr_decoded && !debug_done) begin
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$display("DEBUGGER %0d: [%d] start debugger cycle", i_phase, i_cycle_ctr);
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o_debug_cycle <= 1'b1;
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registers_ctr <= 9'd0;
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registers_state <= `DBG_REG_PC_STR;
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end
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/*
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* generates the registers string
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* 0123456789012
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* PC: xxxxx Carry: x h: @E@ rp: x RSTK7: xxxxx
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* P: x HST: bbbb ST: bbbbbbbbbbbbbbbb RSTK6: xxxxx
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* A: xxxxxxxxxxxxxxxx R0: xxxxxxxxxxxxxxxx RSTK5: xxxxx
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* B: xxxxxxxxxxxxxxxx R1: xxxxxxxxxxxxxxxx RSTK4: xxxxx
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* C: xxxxxxxxxxxxxxxx R2: xxxxxxxxxxxxxxxx RSTK3: xxxxx
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* D: xxxxxxxxxxxxxxxx R3: xxxxxxxxxxxxxxxx RSTK2: xxxxx
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* D0: xxxxx D1: xxxxx R4: xxxxxxxxxxxxxxxx RSTK1: xxxxx
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* RSTK0: xxxxx
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0123456789012345678901234567890123456789012345
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*
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*/
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if (o_debug_cycle && !debug_done) begin
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// $display("DEBUGGER %0d: [%d] debugger %0d", i_phase, i_cycle_ctr, registers_ctr);
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case (registers_state)
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`DBG_REG_PC_STR:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= 8'd10;
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6'd1: registers_str[registers_ctr] <= 8'd13;
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6'd2: registers_str[registers_ctr] <= "P";
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6'd3: registers_str[registers_ctr] <= "C";
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6'd4: registers_str[registers_ctr] <= ":";
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6'd5: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd5) begin
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registers_reg_ptr <= 6'd4;
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registers_state <= `DBG_REG_PC_VALUE;
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end
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end
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`DBG_REG_PC_VALUE:
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begin
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registers_str[registers_ctr] <= hex[i_current_pc[(registers_reg_ptr)*4+:4]];
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registers_reg_ptr <= registers_reg_ptr - 6'd1;
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if (registers_reg_ptr == 6'd0) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_PC_SPACES;
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end
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end
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`DBG_REG_PC_SPACES:
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begin
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registers_str[registers_ctr] <= " ";
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd12) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_CARRY;
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end
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end
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`DBG_REG_CARRY:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= "C";
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6'd1: registers_str[registers_ctr] <= "a";
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6'd2: registers_str[registers_ctr] <= "r";
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6'd3: registers_str[registers_ctr] <= "r";
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6'd4: registers_str[registers_ctr] <= "y";
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6'd5: registers_str[registers_ctr] <= ":";
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6'd6: registers_str[registers_ctr] <= " ";
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6'd7: registers_str[registers_ctr] <= hex[{3'b000,carry}];
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6'd8: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd8) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_CALC_MODE;
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end
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end
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`DBG_REG_CALC_MODE:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= "h";
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6'd1: registers_str[registers_ctr] <= ":";
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6'd2: registers_str[registers_ctr] <= " ";
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6'd3: registers_str[registers_ctr] <= i_reg_alu_mode?"D":"H";
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6'd4: registers_str[registers_ctr] <= "E";
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6'd5: registers_str[registers_ctr] <= i_reg_alu_mode?"C":"X";
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6'd6: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd6) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_RSTK_PTR;
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end
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end
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`DBG_REG_RSTK_PTR:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= "r";
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6'd1: registers_str[registers_ctr] <= "p";
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6'd2: registers_str[registers_ctr] <= ":";
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6'd3: registers_str[registers_ctr] <= " ";
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6'd4: registers_str[registers_ctr] <= hex[{1'b0, i_reg_rstk_ptr}];
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6'd5: registers_str[registers_ctr] <= " ";
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6'd6: registers_str[registers_ctr] <= " ";
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6'd7: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd7) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_RSTK7_STR;
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end
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end
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`DBG_REG_RSTK7_STR:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= "R";
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6'd1: registers_str[registers_ctr] <= "S";
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6'd2: registers_str[registers_ctr] <= "T";
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6'd3: registers_str[registers_ctr] <= "K";
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6'd4: registers_str[registers_ctr] <= "7";
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6'd5: registers_str[registers_ctr] <= ":";
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6'd6: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd6) begin
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registers_reg_ptr <= 6'd4;
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o_dbg_rstk_ptr <= 3'd7;
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registers_state <= `DBG_REG_RSTK7_VALUE;
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end
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end
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`DBG_REG_RSTK7_VALUE:
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begin
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registers_str[registers_ctr] <= hex[i_dbg_rstk_val[(registers_reg_ptr)*4+:4]];
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registers_reg_ptr <= registers_reg_ptr - 6'd1;
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if (registers_reg_ptr == 6'd0) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_P;
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end
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end
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`DBG_REG_P:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= 8'd10;
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6'd1: registers_str[registers_ctr] <= 8'd13;
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6'd2: registers_str[registers_ctr] <= "P";
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6'd3: registers_str[registers_ctr] <= ":";
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6'd4: registers_str[registers_ctr] <= " ";
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6'd5: registers_str[registers_ctr] <= " ";
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6'd6: registers_str[registers_ctr] <= hex[i_reg_p];
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6'd7: registers_str[registers_ctr] <= " ";
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6'd8: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd8) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_HST;
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end
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end
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`DBG_REG_HST:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= "H";
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6'd1: registers_str[registers_ctr] <= "S";
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6'd2: registers_str[registers_ctr] <= "T";
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6'd3: registers_str[registers_ctr] <= ":";
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6'd4: registers_str[registers_ctr] <= " ";
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6'd5: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[3]}];
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6'd6: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[2]}];
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6'd7: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[1]}];
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6'd8: registers_str[registers_ctr] <= hex[{3'b000, i_reg_hst[0]}];
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd8) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_HST_SPACES;
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end
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end
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`DBG_REG_HST_SPACES:
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begin
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registers_str[registers_ctr] <= " ";
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd5) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_ST_STR;
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end
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end
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`DBG_REG_ST_STR:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= "S";
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6'd1: registers_str[registers_ctr] <= "T";
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6'd2: registers_str[registers_ctr] <= ":";
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6'd3: registers_str[registers_ctr] <= " ";
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6'd4: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd4) begin
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registers_reg_ptr <= 6'd15;
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registers_state <= `DBG_REG_ST_VALUE;
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end
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end
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`DBG_REG_ST_VALUE:
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begin
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registers_str[registers_ctr] <= hex[{3'b000, i_reg_st[registers_reg_ptr[3:0]]}];
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registers_reg_ptr <= registers_reg_ptr - 6'd1;
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if (registers_reg_ptr == 6'd0) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_ST_SPACES;
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end
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end
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`DBG_REG_ST_SPACES:
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begin
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registers_str[registers_ctr] <= " ";
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd2) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_RSTK6_STR;
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end
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end
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`DBG_REG_RSTK6_STR:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= "R";
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6'd1: registers_str[registers_ctr] <= "S";
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6'd2: registers_str[registers_ctr] <= "T";
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6'd3: registers_str[registers_ctr] <= "K";
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6'd4: registers_str[registers_ctr] <= "6";
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6'd5: registers_str[registers_ctr] <= ":";
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6'd6: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd6) begin
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registers_reg_ptr <= 6'd4;
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o_dbg_rstk_ptr <= 3'd6;
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registers_state <= `DBG_REG_RSTK6_VALUE;
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end
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end
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`DBG_REG_RSTK6_VALUE:
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begin
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registers_str[registers_ctr] <= hex[i_dbg_rstk_val[(registers_reg_ptr)*4+:4]];
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registers_reg_ptr <= registers_reg_ptr - 6'd1;
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if (registers_reg_ptr == 6'd0) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_C_STR;
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end
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end
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`DBG_REG_C_STR:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= 8'd10;
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6'd1: registers_str[registers_ctr] <= 8'd13;
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6'd2: registers_str[registers_ctr] <= "C";
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6'd3: registers_str[registers_ctr] <= ":";
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6'd4: registers_str[registers_ctr] <= " ";
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6'd5: registers_str[registers_ctr] <= " ";
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd5) begin
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registers_reg_ptr <= 6'd15;
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o_dbg_register <= `ALU_REG_C;
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registers_state <= `DBG_REG_C_VALUE;
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end
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end
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`DBG_REG_C_VALUE:
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begin
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registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
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registers_reg_ptr <= registers_reg_ptr - 6'd1;
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if (registers_reg_ptr == 6'd0) begin
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|
registers_reg_ptr <= 6'd0;
|
|
o_dbg_register <= `ALU_REG_NONE;
|
|
registers_state <= `DBG_REG_SPACES_7;
|
|
end
|
|
end
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|
`DBG_REG_SPACES_7:
|
|
begin
|
|
case (registers_reg_ptr)
|
|
6'd0: registers_str[registers_ctr] <= 8'd10;
|
|
6'd1: registers_str[registers_ctr] <= 8'd13;
|
|
default: registers_str[registers_ctr] <= " ";
|
|
endcase
|
|
registers_reg_ptr <= registers_reg_ptr + 6'd1;
|
|
if (registers_reg_ptr == 6'd47) begin
|
|
registers_reg_ptr <= 6'd0;
|
|
registers_state <= `DBG_REG_RSTK0_STR;
|
|
end
|
|
end
|
|
`DBG_REG_RSTK0_STR:
|
|
begin
|
|
case (registers_reg_ptr)
|
|
6'd0: registers_str[registers_ctr] <= "R";
|
|
6'd1: registers_str[registers_ctr] <= "S";
|
|
6'd2: registers_str[registers_ctr] <= "T";
|
|
6'd3: registers_str[registers_ctr] <= "K";
|
|
6'd4: registers_str[registers_ctr] <= "0";
|
|
6'd5: registers_str[registers_ctr] <= ":";
|
|
6'd6: registers_str[registers_ctr] <= " ";
|
|
endcase
|
|
registers_reg_ptr <= registers_reg_ptr + 6'd1;
|
|
if (registers_reg_ptr == 6'd6) begin
|
|
registers_reg_ptr <= 6'd4;
|
|
o_dbg_rstk_ptr <= 3'd0;
|
|
registers_state <= `DBG_REG_RSTK0_VALUE;
|
|
end
|
|
end
|
|
`DBG_REG_RSTK0_VALUE:
|
|
begin
|
|
registers_str[registers_ctr] <= hex[i_dbg_rstk_val[(registers_reg_ptr)*4+:4]];
|
|
registers_reg_ptr <= registers_reg_ptr - 6'd1;
|
|
if (registers_reg_ptr == 6'd0) begin
|
|
registers_reg_ptr <= 6'd0;
|
|
registers_state <= `DBG_REG_NL_7;
|
|
end
|
|
end
|
|
`DBG_REG_NL_7:
|
|
begin
|
|
case (registers_reg_ptr)
|
|
6'd0: registers_str[registers_ctr] <= 8'd10;
|
|
6'd1: registers_str[registers_ctr] <= 8'd13;
|
|
endcase
|
|
registers_reg_ptr <= registers_reg_ptr + 6'd1;
|
|
if (registers_reg_ptr == 6'd1) begin
|
|
registers_reg_ptr <= 6'd0;
|
|
registers_state <= `DBG_REG_END;
|
|
end
|
|
end
|
|
`DBG_REG_END: begin end
|
|
default: begin $display("ERROR, unknown register state %0d", registers_state); end
|
|
endcase
|
|
if (registers_state == `DBG_REG_END)
|
|
registers_done <= 1'b1;
|
|
else
|
|
registers_ctr <= registers_ctr + 9'd1;
|
|
end
|
|
|
|
/*
|
|
*
|
|
*/
|
|
|
|
if (i_clk_en && o_debug_cycle && debug_done && !write_out) begin
|
|
$display("DEBUGGER %0d: [%d] end debugger cycle", i_phase, i_cycle_ctr);
|
|
counter <= 9'd0;
|
|
write_out <= 1'b1;
|
|
end
|
|
|
|
/* writes the chars to the serial port */
|
|
if (write_out && !o_char_valid && !i_serial_busy) begin
|
|
o_char_send <= ~o_char_send;
|
|
o_char_to_send <= registers_str[counter];
|
|
o_char_valid <= 1'b1;
|
|
counter <= counter + 9'd1;
|
|
`ifdef SIM
|
|
$write("%c", registers_str[counter]);
|
|
`endif
|
|
if (counter == registers_ctr) begin
|
|
`ifdef SIM
|
|
$display("$ %0d chars written", counter + 9'd1);
|
|
`endif
|
|
write_out <= 1'b0;
|
|
registers_done <= 1'b0;
|
|
o_debug_cycle <= 1'b0;
|
|
end
|
|
end
|
|
|
|
if (i_bus_read_valid) begin
|
|
o_char_send <= ~o_char_send;
|
|
o_char_to_send <= hex[i_bus_nibble_in];
|
|
o_char_valid <= 1'b1;
|
|
end
|
|
|
|
if (i_clk_en && i_instr_decoded) begin
|
|
o_char_send <= ~o_char_send;
|
|
o_char_to_send <= "|";
|
|
o_char_valid <= 1'b1;
|
|
end
|
|
|
|
/* clear the char clock enable */
|
|
if (o_char_valid) begin
|
|
o_char_valid <= 1'b0;
|
|
end
|
|
|
|
if (i_reset) begin
|
|
o_debug_cycle <= 1'b0;
|
|
counter <= 9'b0;
|
|
registers_ctr <= 9'd0;
|
|
registers_state <= `DBG_REG_PC_STR;
|
|
registers_reg_ptr <= 6'b0;
|
|
o_dbg_register <= `ALU_REG_NONE;
|
|
registers_done <= 1'b0;
|
|
write_out <= 1'b0;
|
|
o_char_valid <= 1'b0;
|
|
end
|
|
|
|
end
|
|
|
|
endmodule
|
|
|