Commit graph

  • ff04360005 fix missing declaration fix driver conflict Raphael Jacquot 2019-03-03 07:31:18 +0100
  • b3d72c1d3b add some more debugging functionnality segregate reading of the rom in it's own little world Raphaël Jacquot 2019-03-03 07:25:22 +0100
  • 006b663147 implement hex->ascii conversion with a table Raphaël Jacquot 2019-03-03 06:57:14 +0100
  • 182623e043 remove char counting aid Raphael Jacquot 2019-03-02 22:48:34 +0100
  • 21ad359673 fix compiling fix the way the bus controller program worked, which generated evil inferred latches Raphael Jacquot 2019-03-02 22:33:58 +0100
  • 42e8a146ce start implementing some type of debugging functionnality Raphaël Jacquot 2019-03-02 21:45:38 +0100
  • 2fcd9f7b23 decode our first instruction execute said instruction start implementing the debugging engine to see what we are doing Raphaël Jacquot 2019-03-02 19:40:31 +0100
  • c75b33a64a update readme Raphaël Jacquot 2019-03-02 17:06:23 +0100
  • c5355b4a90 enough was done to start feeding the decoder Raphael Jacquot 2019-03-02 15:52:56 +0100
  • cd2b74dcc8 add some commenting Raphael Jacquot 2019-03-02 15:01:00 +0100
  • 3cbd6ac5e1 we are now up to reading the first instruction nibbles Raphael Jacquot 2019-03-02 14:38:01 +0100
  • 8ce2d2a993 implement more of the bus controller Raphael Jacquot 2019-03-02 13:22:09 +0100
  • 15f9b03321 remove product file Raphael Jacquot 2019-02-25 09:51:51 +0100
  • e761f984c8 implement the basic rom, and add a few things Raphael Jacquot 2019-02-25 09:17:17 +0100
  • 8866b8c175 starts complete rewrite Raphael Jacquot 2019-02-24 23:30:57 +0100
  • 570807cf61 time to start over, this this is broken beyond fiddling Raphael Jacquot 2019-02-24 21:54:15 +0100
  • 49b20d72f3 restore RTN / RTNCC / RTNSC Raphael Jacquot 2019-02-23 06:57:48 +0100
  • 7376c920bc change the clock phase generation from a counter to a shift register adapt everywhere needed Raphael Jacquot 2019-02-22 19:30:53 +0100
  • 8725b736b5 attempt to change things according to ylamarre Raphael Jacquot 2019-02-22 18:38:09 +0100
  • 6126bddc90 C=P n and SETHEX / SETDEC Raphael Jacquot 2019-02-22 16:49:06 +0100
  • ebbea44c50 add clearing HST Raphael Jacquot 2019-02-22 16:37:35 +0100
  • 390bdcd22f simplify things in the ALU Raphael Jacquot 2019-02-22 15:48:11 +0100
  • 2028715939 implement PC related functionnality, relative and absolute jumps Raphael Jacquot 2019-02-22 12:00:23 +0100
  • 93d786c2c1 alu rewrite in progress Raphael Jacquot 2019-02-22 08:22:32 +0100
  • 93c856666e modify the alu to make it faster for certain operations. Raphael Jacquot 2019-02-21 22:44:55 +0100
  • 7e6250f59b fix off-by-one error in write loop Raphael Jacquot 2019-02-21 17:10:03 +0100
  • 30d7e6c8df entirely rework the DP_WRITE and WRITE_DP case Raphael Jacquot 2019-02-21 16:55:08 +0100
  • 7d63f0f57a cleanups and move things around Raphael Jacquot 2019-02-20 17:36:21 +0100
  • 70ddc7f9b6 cleanups of the bus controller (more to do) Raphael Jacquot 2019-02-20 16:21:39 +0100
  • ec9c39150d start rewriting logical equations to make them cleaner (oh my this is hard) Raphael Jacquot 2019-02-20 09:20:16 +0100
  • 7088a8dcc7 add copyright Raphael Jacquot 2019-02-20 09:19:00 +0100
  • 1e136010c9 add copyright and license add the 9x block (needs work) Raphael Jacquot 2019-02-20 09:18:40 +0100
  • 62a1624846 add license add some testing stuff, not compelling :-( Raphael Jacquot 2019-02-20 09:17:37 +0100
  • 98d05d318f add copyright and license (oops) Raphael Jacquot 2019-02-20 09:15:22 +0100
  • 380ef1a425 complete rewrite Raphael Jacquot 2019-02-19 16:17:35 +0100
  • 7cbdbcbae1 revise some enable wires Raphael Jacquot 2019-02-19 16:17:16 +0100
  • 51e7fc792c nothing notable Raphael Jacquot 2019-02-19 16:16:53 +0100
  • 2fb29bcd9d add more instruction blocks Raphael Jacquot 2019-02-19 16:16:32 +0100
  • 5c5d24f189 support some more jump instructions Raphael Jacquot 2019-02-19 16:16:18 +0100
  • f1971c3bfe add more instructions Raphael Jacquot 2019-02-19 16:16:00 +0100
  • 443e4d89ff add some instructions and debug Raphael Jacquot 2019-02-19 16:15:46 +0100
  • 6bb654944f move the test rom to a separate module Raphael Jacquot 2019-02-19 16:15:03 +0100
  • 4cce55e4ba initialize all registers, implement jmp_rel2 cleanup the controller some more prepare the core to be rewired add support for block Bx Raphael Jacquot 2019-02-18 17:38:25 +0100
  • 4418ed5824 save one cycle on P= n Raphael Jacquot 2019-02-18 11:36:39 +0100
  • f660168393 cleanup the simulated rom interface Raphael Jacquot 2019-02-18 11:36:28 +0100
  • 1444baca19 implement read from DP Raphael Jacquot 2019-02-18 07:43:36 +0100
  • 0a45b014d7 moved main registers to arrays, makes things much simpler and better, it seems Raphael Jacquot 2019-02-17 23:05:33 +0100
  • 01429b4493 tested all the way to cycle 400 where transfers from memory need to be fixed in the bus controller Raphael Jacquot 2019-02-17 21:20:18 +0100
  • 5c4bff0b5e rewrite the messy hadling of load_dp and dp_write Raphael Jacquot 2019-02-17 20:23:43 +0100
  • 0d3c3ecd3e implement CONFIG cleanup the bus controller Raphael Jacquot 2019-02-17 19:29:39 +0100
  • 7a3a36bd25 implement the reset bus command Raphael Jacquot 2019-02-17 15:03:36 +0100
  • 1c719a1828 cleanup and reorganization for readability Raphael Jacquot 2019-02-17 12:57:38 +0100
  • 8fc7cde507 implement the pieces to replicate the bus data transfers for writing data out. Raphael Jacquot 2019-02-17 12:05:38 +0100
  • 128921c364 start implementing the bus controller Raphael Jacquot 2019-02-17 08:35:26 +0100
  • 500e013bf5 start on the bus controller Raphael Jacquot 2019-02-16 22:38:44 +0100
  • 781d15e0c7 hide some display instructions Raphael Jacquot 2019-02-16 12:26:24 +0100
  • ea3f53f70d implement calculations for # test modify calculations for the unconditional jump and reload PC condition Raphael Jacquot 2019-02-16 12:17:40 +0100
  • 06f79dca88 implemented decoding of 8Ax block, equality and inequality tests over field A. needs implementing the actual ALU op implemented RTNYES/GOYES((not totally finished) RTNYES works need to find an actual GOYES to test that Raphael Jacquot 2019-02-16 11:08:34 +0100
  • ef90d32971 handle block Cx add some code to handle goyes / rtnyes after the tests Raphael Jacquot 2019-02-16 07:35:06 +0100
  • 551b618098 fix driver conflicts Raphael Jacquot 2019-02-15 17:23:07 +0100
  • 44ca0f4a15 fix driver conflict bug implement exch in ALU fix jump base calculations correct some things in debugger fix fields and registers for some instructions Raphael Jacquot 2019-02-15 16:58:38 +0100
  • 3c44b2ae71 cleanup and a few renames Raphael Jacquot 2019-02-15 11:55:58 +0100
  • 343f1e2247 separate block 8 as it's going to be rather large Raphael Jacquot 2019-02-15 11:04:01 +0100
  • 25385115e0 separate the decoder in multiple files, it was becoming unwiedly ;-) Raphael Jacquot 2019-02-15 10:47:00 +0100
  • 1f01d9bdb9 implement block Abx Raphael Jacquot 2019-02-15 09:01:57 +0100
  • 4147a836d2 add stuff for memory transfers Raphael Jacquot 2019-02-15 09:00:44 +0100
  • e1f099145e add register 0 Raphael Jacquot 2019-02-15 09:00:00 +0100
  • ff021e7618 add a feature to complain about not documented things start of handling Ax block Raphael Jacquot 2019-02-15 07:09:07 +0100
  • 235dbfa913 add some wires Raphael Jacquot 2019-02-15 07:08:11 +0100
  • 8b985acc8a add setting HEX or DEC mode fix some cases not covered warnings add handling of RTN instructions Raphael Jacquot 2019-02-15 07:07:55 +0100
  • e72fe301b0 add some definitions for bits in HST register Raphael Jacquot 2019-02-15 07:06:07 +0100
  • 96daffd25c implement CLRHST and friends Raphael Jacquot 2019-02-14 22:54:54 +0100
  • 4b7e59fa21 implement more instructions Raphael Jacquot 2019-02-14 22:14:52 +0100
  • 94ab98a175 remove old useless code fix some verilator reported bugs Raphael Jacquot 2019-02-14 15:27:17 +0100
  • fd69407de0 alu coming up nicely, decoder gaining weight Raphael Jacquot 2019-02-14 14:35:23 +0100
  • f076cf6fb9 start the groundwork to implement jumps move PC handling into the ALU Raphael Jacquot 2019-02-14 08:59:04 +0100
  • 2e2d9108a8 the ALU machine seems to work Raphael Jacquot 2019-02-13 23:18:50 +0100
  • 713e9b967b start implementing the ALU Raphael Jacquot 2019-02-13 22:43:04 +0100
  • aa1d8efd85 finished blocks 1, 2 and 3 Raphael Jacquot 2019-02-13 20:09:25 +0100
  • c357160ab3 start memory transfers Raphael Jacquot 2019-02-13 08:21:25 +0100
  • 2f813cc3a1 missing output in port Raphael Jacquot 2019-02-13 00:19:47 +0100
  • 8858d08bb6 impement 1[012]x Raphael Jacquot 2019-02-12 23:26:18 +0100
  • 466fabe58b major changes in the fields decoder Raphael Jacquot 2019-02-12 21:43:54 +0100
  • 3fad39756f make more wires to remove if levels Raphael Jacquot 2019-02-12 17:29:13 +0100
  • 1f66e782c1 hack in some wires to make things faster Raphael Jacquot 2019-02-12 16:06:13 +0100
  • eef2d13c60 add the block to setup registers for 0Efx Raphael Jacquot 2019-02-12 15:33:04 +0100
  • e409021f35 need more registers ;-) Raphael Jacquot 2019-02-12 15:12:19 +0100
  • bb633d5b80 work on more instructions set fields / registers Raphael Jacquot 2019-02-12 14:51:00 +0100
  • 13e390e8a6 add a few registers Raphael Jacquot 2019-02-12 14:50:24 +0100
  • 81f859eb5d add testing for yosys out status Raphael Jacquot 2019-02-12 14:50:13 +0100
  • 115d3a2544 add instructions to test Raphael Jacquot 2019-02-12 14:49:53 +0100
  • 185fe3d686 remove debug line Raphael Jacquot 2019-02-12 14:49:43 +0100
  • bc4342cc23 fixups Raphael Jacquot 2019-02-12 14:49:33 +0100
  • 88620f217c start handling ALU related stuff Raphael Jacquot 2019-02-12 12:43:36 +0100
  • bcb44743de add required bits to decode fields tables Raphael Jacquot 2019-02-12 11:22:55 +0100
  • d7894d7963 add handling of fields_f table (no decode yet) Raphael Jacquot 2019-02-12 08:56:15 +0100
  • 407b0c6d8d implement jump to block_0Ex Raphael Jacquot 2019-02-12 08:48:13 +0100
  • 3136a4c37b added tentative decoder stall support Raphael Jacquot 2019-02-12 08:21:32 +0100
  • c7cc7f417b refactor as it was getting too complicated secret seems to limit the levels of imbricated ifs... added SETHEX SETDEC RSTK=C C=RSTK Raphael Jacquot 2019-02-12 07:48:25 +0100
  • d4c67cf8fc finally, something that is synthesizable ! Raphael Jacquot 2019-02-12 00:07:12 +0100