mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-20 10:26:31 +01:00
moved main registers to arrays, makes things much simpler and better, it seems
This commit is contained in:
Raphael Jacquot
parent
01429b4493
commit
0a45b014d7
3 changed files with 114 additions and 55 deletions
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@ -38,3 +38,6 @@ second delay is posedge $glbnet$clk -> <async>
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2019-02-17 15:11 1677 70.29MHz 34.92ns 13.01ns 11788 74.69MHz 17.42ns 3.88ns
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2019-02-17 19:30 1637 74.68MHz 34.80ns 12.77ns 11687 68.49Mhz 18.03ns 4.01ns
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2019-02-17 20:25 1733 72.37MHz 32.87ns 12.77ns 12213 73.52MHz 16.22ns 3.87ns
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2019-02-17 21:21 1734 71.16MHz 32.10ns 12.05ns 11359 73.56MHz 17.19ns 3.73ns
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2019-02-17 22:31 1573 77.32MHz 32.91ns 12.77ns 10265 70.53MHz 17.35ns 4.13ns
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2019-02-17 22:48 1067 69.94MHz 32.87ns 12.77ns 6427 74.33MHz 17.71ns 3.96ns
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164
saturn_alu.v
164
saturn_alu.v
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@ -171,16 +171,17 @@ reg [19:0] PC;
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reg [19:0] D0;
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reg [19:0] D1;
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reg [63:0] A;
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reg [63:0] B;
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reg [63:0] C;
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reg [63:0] D;
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//reg [63:0] A;
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reg [3:0] A[0:15];
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reg [3:0] B[0:15];
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reg [3:0] C[0:15];
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reg [3:0] D[0:15];
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reg [63:0] R0;
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reg [63:0] R1;
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reg [63:0] R2;
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reg [63:0] R3;
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reg [63:0] R4;
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reg [3:0] R0[0:15];
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reg [3:0] R1[0:15];
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reg [3:0] R2[0:15];
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reg [3:0] R3[0:15];
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reg [3:0] R4[0:15];
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reg [0:0] CARRY;
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reg [0:0] DEC;
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@ -320,6 +321,10 @@ assign is_alu_op_test = ((alu_op == `ALU_OP_TEST_EQ) ||
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*
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****************************************************************************/
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`ifdef SIM
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reg [4:0] alu_dbg_ctr;
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`endif
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always @(posedge i_clk) begin
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`ifdef SIM
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@ -345,12 +350,43 @@ always @(posedge i_clk) begin
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PC, CARRY, DEC?"DEC":"HEX", rstk_ptr, RSTK[7]);
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$display("P: %h HST: %b ST: %b RSTK6: %5h",
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P, HST, ST, RSTK[6]);
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$display("A: %h R0: %h RSTK5: %5h", A, R0, RSTK[5]);
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$display("B: %h R1: %h RSTK4: %5h", B, R1, RSTK[4]);
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$display("C: %h R2: %h RSTK3: %5h", C, R2, RSTK[3]);
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$display("D: %h R3: %h RSTK2: %5h", D, R3, RSTK[2]);
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$display("D0: %h D1: %h R4: %h RSTK1: %5h",
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D0, D1, R4, RSTK[1]);
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$write("A: ");
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", A[alu_dbg_ctr]);
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$write(" R0: ");
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", R0[alu_dbg_ctr]);
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$write(" RSTK5: %5h\n", RSTK[5]);
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$write("B: ");
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", B[alu_dbg_ctr]);
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$write(" R1: ");
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", R1[alu_dbg_ctr]);
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$write(" RSTK4: %5h\n", RSTK[4]);
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$write("C: ");
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", C[alu_dbg_ctr]);
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$write(" R2: ");
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", R2[alu_dbg_ctr]);
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$write(" RSTK3: %5h\n", RSTK[3]);
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$write("D: ");
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", D[alu_dbg_ctr]);
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$write(" R3: ");
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", R3[alu_dbg_ctr]);
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$write(" RSTK2: %5h\n", RSTK[2]);
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$write("D0: %h D1: %h R4: ", D0, D1);
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for(alu_dbg_ctr=15;alu_dbg_ctr!=31;alu_dbg_ctr=alu_dbg_ctr-1)
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$write("%h", R4[alu_dbg_ctr]);
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$write(" RSTK1: %5h\n", RSTK[1]);
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$display(" ADDR: %5h RSTK0: %5h",
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o_bus_address, RSTK[0]);
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end
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@ -457,33 +493,38 @@ always @(posedge i_clk) begin
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* source 1
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*/
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case (alu_op)
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`ALU_OP_ZERO: begin end // no source required
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`ALU_OP_COPY,
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`ALU_OP_EXCH,
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`ALU_OP_RST_BIT,
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`ALU_OP_SET_BIT,
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`ALU_OP_2CMPL,
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`ALU_OP_ADD,
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`ALU_OP_TEST_EQ,
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`ALU_OP_TEST_NEQ,
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`ALU_OP_JMP_REL3,
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`ALU_OP_JMP_REL4,
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`ALU_OP_JMP_ABS5,
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`ALU_OP_CLR_MASK:
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case (reg_src1)
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`ALU_REG_A: p_src1 <= A [f_cur*4+:4];
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`ALU_REG_B: p_src1 <= B [f_cur*4+:4];
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`ALU_REG_C: p_src1 <= C [f_cur*4+:4];
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`ALU_REG_D: p_src1 <= D [f_cur*4+:4];
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`ALU_REG_D0: p_src1 <= D0[f_cur*4+:4];
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`ALU_REG_D1: p_src1 <= D1[f_cur*4+:4];
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`ALU_REG_P: p_src1 <= P;
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`ALU_REG_HST: p_src1 <= HST;
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`ALU_REG_IMM: p_src1 <= i_imm_value;
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`ALU_REG_ZERO: p_src1 <= 0;
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default: $display("#### SRC_1 UNHANDLED REGISTER %0d", reg_src1);
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endcase
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default: $display("#### SRC_1 UNHANDLED OPERATION %0d", alu_op);
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`ALU_OP_ZERO: begin end // no source required
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`ALU_OP_COPY,
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`ALU_OP_EXCH,
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`ALU_OP_RST_BIT,
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`ALU_OP_SET_BIT,
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`ALU_OP_2CMPL,
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`ALU_OP_ADD,
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`ALU_OP_TEST_EQ,
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`ALU_OP_TEST_NEQ,
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`ALU_OP_JMP_REL3,
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`ALU_OP_JMP_REL4,
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`ALU_OP_JMP_ABS5,
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`ALU_OP_CLR_MASK:
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case (reg_src1)
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`ALU_REG_A: p_src1 <= A[f_cur];
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`ALU_REG_B: p_src1 <= B[f_cur];
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`ALU_REG_C: p_src1 <= C[f_cur];
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`ALU_REG_D: p_src1 <= D[f_cur];
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`ALU_REG_R0: p_src1 <= R0[f_cur];
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`ALU_REG_R1: p_src1 <= R1[f_cur];
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`ALU_REG_R2: p_src1 <= R2[f_cur];
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`ALU_REG_R3: p_src1 <= R3[f_cur];
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`ALU_REG_R4: p_src1 <= R4[f_cur];
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`ALU_REG_D0: p_src1 <= D0[f_cur*4+:4];
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`ALU_REG_D1: p_src1 <= D1[f_cur*4+:4];
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`ALU_REG_P: p_src1 <= P;
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`ALU_REG_HST: p_src1 <= HST;
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`ALU_REG_IMM: p_src1 <= i_imm_value;
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`ALU_REG_ZERO: p_src1 <= 0;
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default: $display("#### SRC_1 UNHANDLED REGISTER %0d", reg_src1);
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endcase
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default: $display("#### SRC_1 UNHANDLED OPERATION %0d", alu_op);
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endcase
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@ -505,10 +546,15 @@ always @(posedge i_clk) begin
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`ALU_OP_TEST_NEQ,
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`ALU_OP_CLR_MASK: begin
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case (reg_src2)
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`ALU_REG_A: p_src2 <= A [f_cur*4+:4];
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`ALU_REG_B: p_src2 <= B [f_cur*4+:4];
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`ALU_REG_C: p_src2 <= C [f_cur*4+:4];
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`ALU_REG_D: p_src2 <= D [f_cur*4+:4];
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`ALU_REG_A: p_src2 <= A[f_cur];
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`ALU_REG_B: p_src2 <= B[f_cur];
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`ALU_REG_C: p_src2 <= C[f_cur];
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`ALU_REG_D: p_src2 <= D[f_cur];
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`ALU_REG_R0: p_src2 <= R0[f_cur];
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`ALU_REG_R1: p_src2 <= R1[f_cur];
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`ALU_REG_R2: p_src2 <= R2[f_cur];
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`ALU_REG_R3: p_src2 <= R3[f_cur];
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`ALU_REG_R4: p_src2 <= R4[f_cur];
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`ALU_REG_D0: p_src2 <= D0[f_cur*4+:4];
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`ALU_REG_D1: p_src2 <= D1[f_cur*4+:4];
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`ALU_REG_P: p_src2 <= P;
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@ -653,10 +699,15 @@ always @(posedge i_clk) begin
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`ALU_OP_ADD,
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`ALU_OP_CLR_MASK:
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case (reg_dest)
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`ALU_REG_A: A[f_cur*4+:4] <= c_res1;
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`ALU_REG_B: B[f_cur*4+:4] <= c_res1;
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`ALU_REG_C: C[f_cur*4+:4] <= c_res1;
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`ALU_REG_D: D[f_cur*4+:4] <= c_res1;
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`ALU_REG_A: A[f_cur] <= c_res1;
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`ALU_REG_B: B[f_cur] <= c_res1;
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`ALU_REG_C: C[f_cur] <= c_res1;
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`ALU_REG_D: D[f_cur] <= c_res1;
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`ALU_REG_R0: R0[f_cur] <= c_res1;
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`ALU_REG_R1: R1[f_cur] <= c_res1;
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`ALU_REG_R2: R2[f_cur] <= c_res1;
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`ALU_REG_R3: R3[f_cur] <= c_res1;
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`ALU_REG_R4: R4[f_cur] <= c_res1;
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`ALU_REG_D0: D0[f_cur*4+:4] <= c_res1;
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`ALU_REG_D1: D1[f_cur*4+:4] <= c_res1;
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`ALU_REG_ST: ST[f_cur*4+:4] <= c_res1;
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@ -687,10 +738,15 @@ always @(posedge i_clk) begin
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case (alu_op)
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`ALU_OP_EXCH: // 2nd assign, with src2
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case (reg_src2)
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`ALU_REG_A: A[f_cur*4+:4] <= c_res2;
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`ALU_REG_B: B[f_cur*4+:4] <= c_res2;
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`ALU_REG_C: C[f_cur*4+:4] <= c_res2;
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`ALU_REG_D: D[f_cur*4+:4] <= c_res2;
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`ALU_REG_A: A[f_cur] <= c_res2;
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`ALU_REG_B: B[f_cur] <= c_res2;
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`ALU_REG_C: C[f_cur] <= c_res2;
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`ALU_REG_D: D[f_cur] <= c_res2;
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`ALU_REG_R0: R0[f_cur] <= c_res2;
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`ALU_REG_R1: R1[f_cur] <= c_res2;
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`ALU_REG_R2: R2[f_cur] <= c_res2;
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`ALU_REG_R3: R3[f_cur] <= c_res2;
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`ALU_REG_R4: R4[f_cur] <= c_res2;
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// `ALU_REG_D0: D0[f_start*4+:4] <= c_res2;
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// `ALU_REG_D1: D1[f_start*4+:4] <= c_res2;
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// `ALU_REG_ST: ST[f_start*4+:4] <= c_res2;
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@ -235,7 +235,7 @@ always @(posedge i_clk) begin
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o_bus_data <= `BUSCMD_DP_WRITE;
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last_cmd <= `BUSCMD_DP_WRITE;
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cmd_dp_write_s <= 1;
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o_bus_strobe <= 1;
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o_bus_strobe <= 1;
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end
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