Miroirs/hp-saturn
1
0
Fork 0
mirror of https://github.com/sxpert/hp-saturn synced 2025-01-20 10:26:31 +01:00
Code Issues Projects Releases Packages Wiki Activity

add some instructions and debug

Browse source
This commit is contained in:
Raphael Jacquot 2019-02-19 16:15:46 +01:00
parent 6bb654944f
commit 443e4d89ff
2 changed files with 31 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
saturn_decoder_fields.v
View file

@ -127,13 +127,19 @@ always @(posedge i_clk) begin
end
if (do_block_14x_15xx && !do_fields_table) begin
$display("fields_14x_15xx : dft %b | tv %b | fv %b", do_fields_table, table_value, o_field_valid);
o_field <= i_nibble[3]?`FT_FIELD_B:`FT_FIELD_A;
o_field_start <= 0;
o_field_last <= i_nibble[3]?1:4;
o_field_valid <= 1;
end
if (do_block_14x_15xx && do_fields_table && table_value) begin
if (do_block_14x_15xx && do_fields_table) begin
$display("fields_14x_15xx : dft %b | tv %b | fv %b", do_fields_table, table_value, o_field_valid);
end
if (do_block_15xx && table_value) begin
$display("fields_15xx dft %b | tv %b | fv %b", do_fields_table, table_value, o_field_valid);
o_field_start <= 0;
o_field_last <= i_nibble;
o_field_valid <= 1;

24
saturn_decoder_registers.v
View file

@ -1,4 +1,7 @@
`ifndef _SATURN_DECODER_REGISTERS
`define _SATURN_DECODER_REGISTERS
`include "def-alu.v"
/******************************************************************************
*
@ -167,6 +170,7 @@ always @(posedge i_clk) begin
4'h5: begin
o_reg_dest <= `ALU_REG_ADDR;
o_reg_src1 <= `ALU_REG_C;
o_reg_src2 <= `ALU_REG_NOPE;
end
endcase
end
@ -177,6 +181,24 @@ always @(posedge i_clk) begin
o_reg_src2 <= 0;
end
if (do_block_81Af0x) begin
o_reg_dest <= { 2'b01, i_nibble[2:0]};
o_reg_src1 <= i_nibble[3]?`ALU_REG_C:`ALU_REG_A;
o_reg_src2 <= 0;
end
if (do_block_81Af1x) begin
o_reg_dest <= i_nibble[3]?`ALU_REG_C:`ALU_REG_A;
o_reg_src1 <= { 2'b01, i_nibble[2:0]};
o_reg_src2 <= 0;
end
if (do_block_81Af2x) begin
o_reg_dest <= i_nibble[3]?`ALU_REG_C:`ALU_REG_A;
o_reg_src1 <= i_nibble[3]?`ALU_REG_C:`ALU_REG_A;
o_reg_src2 <= { 2'b01, i_nibble[2:0]};
end
if (do_block_82x) begin
o_reg_dest <= `ALU_REG_HST;
o_reg_src1 <= `ALU_REG_HST;
@ -281,3 +303,5 @@ always @(posedge i_clk) begin
end
end
`endif