Miroirs/hp-saturn
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cleanup and a few renames

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This commit is contained in:
Raphael Jacquot 2019-02-15 11:55:58 +01:00
parent 343f1e2247
commit 3c44b2ae71
5 changed files with 74 additions and 53 deletions
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6
history.txt
View file

@ -1,3 +1,6 @@
first delay is <async> -> posedge $glbnet$clk
second delay is posedge $glbnet$clk -> <async>
cells speed 1 delay (a) 1 delay 1 arcs speed 2 delay (a) 2 delay 2
2019-02-12 07:37 29 490.92MHz 2.68ns 330.14MHz 1.99ns
2019-02-12 07:48 29 490.92MHz 14.34ns 2.20ns 350.39MHz 4.14ns 1.77ns
@ -25,4 +28,5 @@
2019-02-13 23:21 318 113.77MHz 25.44ns 13.97ns 3061 117.75MHz 9.56ns 4.08ns
2019-02-14 09:00 353 118.23MHz 26.00ns 12.28ns 3334 119.40MHz 10.08ns 3.84ns
2019-02-14 22:11 403 115.09MHz 27.38ns 11.32ns 2430 111.51MHz 12.62ns 3.57ns
2019-02-15 07:14 535 97.16MHz 26.57ns 9.16ns 3073 96.10MHz 13.38ns 3.13ns
2019-02-15 07:14 535 97.16MHz 26.57ns 9.16ns 3073 96.10MHz 13.38ns 3.13ns
2019-02-15 11:07 577 102.13MHz 28.63ns 11.09ns 3270 101.77MHz 13.65ns 3.67ns

87
saturn_decoder.v
View file

@ -224,27 +224,36 @@ always @(posedge i_clk) begin
// decoder block states
block_0x <= 0;
block_0Efx <= 0;
block_1x <= 0;
block_save_to_R_W <= 0;
block_rest_from_R_W <= 0;
block_exch_with_R_W <= 0;
block_pointer_assign_exch <= 0;
block_mem_transfer <= 0;
block_pointer_arith_const <= 0;
block_load_p <= 0;
block_load_c_hex <= 0;
// complain if blocks are not clean
`ifdef SIM
if (block_0x) $display("block_0x NOT CLEAN");
if (block_0Efx) $display("block_0Efx NOT CLEAN");
if (block_1x) $display("block_1x NOT CLEAN");
if (block_save_to_R_W) $display("block_save_to_R_W NOT CLEAN");
if (block_rest_from_R_W) $display("block_rest_from_R_W NOT CLEAN");
if (block_exch_with_R_W) $display("block_exch_with_R_W NOT CLEAN");
if (block_pointer_assign_exch) $display("block_pointer_assign_exch NOT CLEAN");
if (block_mem_transfer) $display("block_mem_transfer NOT CLEAN");
if (block_pointer_arith_const) $display("block_pointer_arith_const NOT CLEAN");
if (block_2x) $display("block_2x NOT CLEAN");
if (block_3x) $display("block_load_c_hex NOT CLEAN");
block_8x <= 0;
block_80x <= 0;
block_80Cx <= 0;
block_82x <= 0;
if (block_8x) $display("block_8x NOT CLEAN");
if (block_80x) $display("block_80x NOT CLEAN");
if (block_80Cx) $display("block_80Cx NOT CLEAN");
if (block_82x) $display("block_82x NOT CLEAN");
block_Ax <= 0;
if (block_Ax) $display("block_Ax NOT CLEAN");
block_Fx <= 0;
if (block_Dx) $display("block_Dx NOT CLEAN");
if (block_Fx)
if (block_load_reg_imm) $display("block_load_reg_imm NOT CLEAN");
if (block_jmp) $display("block_jmp NOT CLEAN");
if (block_sr_bit) $display("block_sr_bit NOT CLEAN");
`endif
// decoder subroutine states
block_load_reg_imm <= 0;
@ -280,10 +289,10 @@ always @(posedge i_clk) begin
// assign block regs
case (i_nibble)
4'h0: block_0x <= 1;
4'h1: block_1x <= 1;
4'h2: block_load_p <= 1;
4'h3: block_load_c_hex <= 1;
4'h0: block_0x <= 1;
4'h1: block_1x <= 1;
4'h2: block_2x <= 1;
4'h3: block_3x <= 1;
4'h4, 4'h5: begin
// 400 RTNC
// 420 NOP3
@ -301,12 +310,12 @@ always @(posedge i_clk) begin
4'h6, 4'h7: begin
// 6xxx GOTO
// 7xxx GOSUB
o_alu_no_stall <= 1;
o_alu_op <= `ALU_OP_JMP_REL3;
mem_load_max <= 2;
o_mem_pos <= 0;
o_push <= i_nibble[0];
block_jmp <= 1;
o_alu_no_stall <= 1;
o_alu_op <= `ALU_OP_JMP_REL3;
mem_load_max <= 2;
o_mem_pos <= 0;
o_push <= i_nibble[0];
block_jmp <= 1;
`ifdef SIM
o_unimplemented <= 0;
`endif
@ -319,6 +328,7 @@ always @(posedge i_clk) begin
o_fields_table <= `FT_TABLE_a;
block_Ax <= 1;
end
4'hD: block_Dx <= 1;
4'hF: block_Fx <= 1;
default: begin
`ifdef SIM
@ -392,10 +402,7 @@ always @(posedge i_clk) begin
o_ins_alu_op <= 1;
o_alu_op <= i_nibble[0]?`ALU_OP_DEC:`ALU_OP_INC;
end
4'hE: begin
block_0x <= 0;
o_fields_table <= `FT_TABLE_f;
end
4'hE: o_fields_table <= `FT_TABLE_f;
default: begin
`ifdef SIM
$display("block_0x: nibble %h not handled", i_nibble);
@ -407,6 +414,7 @@ always @(posedge i_clk) begin
block_0Efx <= (i_nibble == 4'hE);
go_fields_table <= (i_nibble == 4'hE);
o_ins_decoded <= (i_nibble != 4'hE);
block_0x <= 0;
end
/******************************************************************************
@ -502,6 +510,7 @@ always @(posedge i_clk) begin
next_nibble <= use_fields_tbl;
use_fields_tbl <= 0;
o_ins_decoded <= !(use_fields_tbl);
block_mem_transfer <= use_fields_tbl;
end
if (do_block_pointer_arith_const) begin
@ -510,25 +519,26 @@ always @(posedge i_clk) begin
o_ins_decoded <= 1;
end
if (do_block_load_p) begin
if (do_block_2x) begin
o_ins_alu_op <= 1;
o_alu_op <= `ALU_OP_COPY;
o_imm_value <= i_nibble;
next_nibble <= 0;
o_ins_decoded <= 1;
o_imm_value <= i_nibble;
next_nibble <= 0;
o_ins_decoded <= 1;
`ifdef SIM
o_unimplemented <= 0;
`endif
block_2x <= 0;
end
if (do_block_load_c_hex) begin
if (do_block_3x) begin
// $write("block load C hex %h\n", i_nibble);
mem_load_max <= i_nibble + 1;
o_mem_pos <= 0;
o_alu_no_stall <= 1;
o_alu_op <= `ALU_OP_COPY;
block_load_reg_imm <= 1;
block_load_c_hex <= 0;
block_3x <= 0;
`ifdef SIM
o_unimplemented <= 0;
`endif
@ -559,6 +569,9 @@ always @(posedge i_clk) begin
block_Abx <= 0;
end
if (do_block_Fx) begin
end
if (do_block_Fx) begin
case (i_nibble)
4'h8, 4'h9, 4'hA, 4'hB: // r=-r A

28
saturn_decoder_block_vars.v
View file

@ -51,23 +51,23 @@ reg block_mem_transfer;
wire do_block_mem_transfer;
assign do_block_mem_transfer = do_on_other_nibbles && block_mem_transfer;
reg block_pointer_arith_const;
wire do_block_pointer_arith_const;
reg block_pointer_arith_const;
wire do_block_pointer_arith_const;
assign do_block_pointer_arith_const = do_on_other_nibbles && block_pointer_arith_const;
reg block_load_p;
wire do_block_load_p;
assign do_block_load_p = do_on_other_nibbles && block_load_p;
reg block_2x;
wire do_block_2x;
assign do_block_2x = do_on_other_nibbles && block_2x;
reg block_load_c_hex;
wire do_block_load_c_hex;
assign do_block_load_c_hex = do_on_other_nibbles && block_load_c_hex;
reg block_3x;
wire do_block_3x;
assign do_block_3x = do_on_other_nibbles && block_3x;
reg block_jmp2_cry_set;
reg block_jmp2_cry_clr;
// reg block_jmp2_cry_set;
// reg block_jmp2_cry_clr;
reg block_8x;
wire do_block_8x;
reg block_8x;
wire do_block_8x;
assign do_block_8x = do_on_other_nibbles && block_8x;
reg block_80x;
@ -94,6 +94,10 @@ reg block_Abx;
wire do_block_Abx;
assign do_block_Abx = do_on_other_nibbles && block_Abx;
reg block_Dx;
wire do_block_Dx;
assign do_block_Dx = do_on_other_nibbles && block_Dx;
reg block_Fx;
wire do_block_Fx;
assign do_block_Fx = do_on_other_nibbles && block_Fx;

2
saturn_decoder_fields.v
View file

@ -135,7 +135,7 @@ always @(posedge i_clk) begin
o_field_last <= 4;
end
if (do_block_load_c_hex) begin
if (do_block_3x) begin
o_field_start <= i_reg_p;
o_field_last <= (i_nibble + i_reg_p) & 4'hF;
end

4
saturn_decoder_registers.v
View file

@ -137,12 +137,12 @@ always @(posedge i_clk) begin
o_reg_src2 <= `ALU_REG_IMM;
end
if (do_block_load_p) begin
if (do_block_2x) begin
o_reg_dest <= `ALU_REG_P;
o_reg_src1 <= `ALU_REG_IMM;
end
if (do_block_load_c_hex) begin
if (do_block_3x) begin
o_reg_dest <= `ALU_REG_C;
o_reg_src1 <= `ALU_REG_IMM;
end