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https://github.com/sxpert/hp-saturn
synced 2024-09-28 15:20:27 +02:00
implement CLRHST and friends
This commit is contained in:
Raphael Jacquot
parent
4b7e59fa21
commit
96daffd25c
3 changed files with 93 additions and 53 deletions
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@ -62,7 +62,7 @@
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//15
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`define ALU_REG_DAT0 16
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`define ALU_REG_DAT1 17
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`define ALU_REG_CST 18
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`define ALU_REG_HST 18
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`define ALU_REG_ST 19
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`define ALU_REG_P 20
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`define ALU_REG_M 21
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66
saturn_alu.v
66
saturn_alu.v
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@ -287,9 +287,9 @@ always @(posedge i_clk) begin
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`ifdef SIM
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if (alu_debug)
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$display({"ALU_INIT 3: run %b | done %b | stall %b | op %d | s %h | l %h ",
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"| ialu %b | dest %d | src1 %d | src2 %d"},
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"| ialu %b | dest %d | src1 %d | src2 %d | imm %h"},
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alu_run, alu_done, o_alu_stall_dec, i_alu_op,i_field_start, i_field_last,
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i_ins_alu_op, i_reg_dest, i_reg_src1, i_reg_src2);
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i_ins_alu_op, i_reg_dest, i_reg_src1, i_reg_src2, i_imm_value);
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`endif
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jump_bse <= PC;
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@ -346,7 +346,8 @@ always @(posedge i_clk) begin
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`ALU_OP_2CMPL,
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`ALU_OP_JMP_REL3,
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`ALU_OP_JMP_REL4,
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`ALU_OP_JMP_ABS5:
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`ALU_OP_JMP_ABS5,
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`ALU_OP_CLR_MASK:
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case (reg_src1)
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`ALU_REG_A: p_src1 <= A [f_start*4+:4];
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`ALU_REG_B: p_src1 <= B [f_start*4+:4];
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@ -355,10 +356,20 @@ always @(posedge i_clk) begin
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`ALU_REG_D0: p_src1 <= D0[f_start*4+:4];
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`ALU_REG_D1: p_src1 <= D1[f_start*4+:4];
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`ALU_REG_P: p_src1 <= P;
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`ALU_REG_HST: p_src1 <= HST;
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`ALU_REG_IMM: p_src1 <= i_imm_value;
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default: $display("####UNHANDLED REGISTER %0d", reg_src1);
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default: $display("#### SRC_1 UNHANDLED REGISTER %0d", reg_src1);
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endcase
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default: $display("####UNHANDLED OPERATION %0d", alu_op);
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default: $display("#### SRC_1 UNHANDLED OPERATION %0d", alu_op);
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endcase
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case (alu_op)
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`ALU_OP_CLR_MASK:
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case (reg_src2)
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`ALU_REG_IMM: p_src2 <= i_imm_value;
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default: $display("#### SRC_2 UNHANDLED REGISTER %0d", reg_src2);
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endcase
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default: $display("#### SRC_2 UNHANDLED OPERATION %0d", alu_op);
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endcase
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// setup p_carry
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@ -401,6 +412,7 @@ always @(posedge i_clk) begin
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`ALU_OP_JMP_REL3,
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`ALU_OP_JMP_REL4,
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`ALU_OP_JMP_ABS5: jump_off[f_start*4+:4] <= p_src1;
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`ALU_OP_CLR_MASK: c_res1 <= p_src1 & ~p_src2;
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endcase
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case (alu_op)
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@ -436,28 +448,32 @@ always @(posedge i_clk) begin
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// (~p_src1) == 4'hf );
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case (alu_op)
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`ALU_OP_ZERO,
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`ALU_OP_COPY,
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`ALU_OP_2CMPL:
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case (reg_dest)
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`ALU_REG_A: A [f_start*4+:4] <= c_res1;
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`ALU_REG_B: B [f_start*4+:4] <= c_res1;
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`ALU_REG_C: C [f_start*4+:4] <= c_res1;
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`ALU_REG_D: D [f_start*4+:4] <= c_res1;
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`ALU_REG_D0: D0[f_start*4+:4] <= c_res1;
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`ALU_REG_D1: D1[f_start*4+:4] <= c_res1;
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`ALU_REG_ST: ST[f_start*4+:4] <= c_res1;
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`ALU_REG_P: P <= c_res1;
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endcase
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`ALU_OP_RST_BIT,
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`ALU_OP_SET_BIT:
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case (reg_dest)
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`ALU_REG_ST: ST[c_res1] <= alu_op==`ALU_OP_SET_BIT?1:0;
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default:
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$display("invalid register for op");
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endcase
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`ALU_OP_ZERO,
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`ALU_OP_COPY,
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`ALU_OP_2CMPL,
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`ALU_OP_CLR_MASK:
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case (reg_dest)
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`ALU_REG_A: A [f_start*4+:4] <= c_res1;
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`ALU_REG_B: B [f_start*4+:4] <= c_res1;
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`ALU_REG_C: C [f_start*4+:4] <= c_res1;
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`ALU_REG_D: D [f_start*4+:4] <= c_res1;
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`ALU_REG_D0: D0[f_start*4+:4] <= c_res1;
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`ALU_REG_D1: D1[f_start*4+:4] <= c_res1;
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`ALU_REG_ST: ST[f_start*4+:4] <= c_res1;
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`ALU_REG_P: P <= c_res1;
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`ALU_REG_HST: HST <= c_res1;
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endcase
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`ALU_OP_RST_BIT,
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`ALU_OP_SET_BIT:
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case (reg_dest)
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`ALU_REG_ST: ST[c_res1] <= alu_op==`ALU_OP_SET_BIT?1:0;
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default: $display("#### ALU_SAVE invalid register %0d for op %0d", reg_dest, alu_op);
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endcase
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default: $display("#### ALU_SAVE UNHANDLED OP %0d", alu_op);
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endcase
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case (alu_op)
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`ALU_OP_2CMPL: CARRY <= !is_zero;
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endcase
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@ -214,31 +214,46 @@ always @(posedge i_clk) begin
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if (o_ins_alu_op) begin
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case (o_alu_op)
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`ALU_OP_JMP_REL3: $write("GOTO");
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`ALU_OP_JMP_REL4: $write("%s", o_push?"GOSUBL":"GOLONG");
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`ALU_OP_JMP_ABS5: $write("%s", o_push?"GOSBVL":"GOVLNG");
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default:
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case (o_reg_dest)
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`ALU_REG_A: $write("A");
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`ALU_REG_B: $write("B");
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`ALU_REG_C:
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if (is_lc_hex) $write("LCHEX");
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else $write("C");
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`ALU_REG_D: $write("D");
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`ALU_REG_D0: $write("D0");
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`ALU_REG_D1: $write("D1");
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`ALU_REG_RSTK: $write("RSTK");
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`ALU_REG_R0: $write("R0");
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`ALU_REG_R1: $write("R1");
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`ALU_REG_R2: $write("R2");
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`ALU_REG_R3: $write("R3");
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`ALU_REG_R4: $write("R4");
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`ALU_REG_DAT0: $write("DAT0");
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`ALU_REG_DAT1: $write("DAT1");
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`ALU_REG_ST: if (o_alu_op!=`ALU_OP_ZERO) $write("ST");
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`ALU_REG_P: $write("P");
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default: $write("[dest:%0d]", o_reg_dest);
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endcase
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`ALU_OP_JMP_REL3: $write("GOTO");
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`ALU_OP_JMP_REL4: $write("%s", o_push?"GOSUBL":"GOLONG");
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`ALU_OP_JMP_ABS5: $write("%s", o_push?"GOSBVL":"GOVLNG");
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`ALU_OP_CLR_MASK:
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case (o_reg_dest)
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`ALU_REG_HST:
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case (o_imm_value)
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4'h1: $write("XM=0");
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4'h2: $write("SB=0");
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4'h4: $write("SR=0");
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4'h8: $write("MP=0");
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default: begin
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$write("CLRHST");
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if (o_imm_value != 4'hF) $write("\t%1h", o_imm_value);
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end
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endcase
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default: $write("[VLR_MASK dest:%0d]", o_reg_dest);
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endcase
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default:
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case (o_reg_dest)
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`ALU_REG_A: $write("A");
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`ALU_REG_B: $write("B");
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`ALU_REG_C:
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if (is_lc_hex) $write("LCHEX");
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else $write("C");
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`ALU_REG_D: $write("D");
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`ALU_REG_D0: $write("D0");
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`ALU_REG_D1: $write("D1");
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`ALU_REG_RSTK: $write("RSTK");
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`ALU_REG_R0: $write("R0");
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`ALU_REG_R1: $write("R1");
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`ALU_REG_R2: $write("R2");
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`ALU_REG_R3: $write("R3");
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`ALU_REG_R4: $write("R4");
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`ALU_REG_DAT0: $write("DAT0");
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`ALU_REG_DAT1: $write("DAT1");
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`ALU_REG_ST: if (o_alu_op!=`ALU_OP_ZERO) $write("ST");
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`ALU_REG_P: $write("P");
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default: $write("[dest:%0d]", o_reg_dest);
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endcase
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endcase
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case (o_alu_op)
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@ -259,7 +274,8 @@ always @(posedge i_clk) begin
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`ALU_OP_EXCH,
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`ALU_OP_JMP_REL3,
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`ALU_OP_JMP_REL4,
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`ALU_OP_JMP_ABS5: begin end
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`ALU_OP_JMP_ABS5,
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`ALU_OP_CLR_MASK: begin end
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default: $write("[op:%0d]", o_alu_op);
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endcase
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@ -365,7 +381,8 @@ always @(posedge i_clk) begin
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else
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case (o_reg_dest)
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`ALU_REG_P,
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`ALU_REG_ST: begin end
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`ALU_REG_ST,
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`ALU_REG_HST: begin end
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`ALU_REG_C:
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if (o_reg_src1 == `ALU_REG_P)
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$write("%0d", o_field_start);
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@ -898,6 +915,7 @@ always @(posedge i_clk) begin
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if (do_block_82x) begin
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o_ins_alu_op <= 1;
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o_alu_op <= `ALU_OP_CLR_MASK;
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o_imm_value <= i_nibble;
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next_nibble <= 0;
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o_ins_decoded <= 1;
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end
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@ -1127,6 +1145,12 @@ always @(posedge i_clk) begin
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o_reg_src2 <= 0;
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end
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if (do_block_82x) begin
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o_reg_dest <= `ALU_REG_HST;
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o_reg_src1 <= `ALU_REG_HST;
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o_reg_src2 <= `ALU_REG_IMM;
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end
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if (do_block_Fx) begin
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case (i_nibble)
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4'h8, 4'h9, 4'hA, 4'hB: begin
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