mirror of
https://github.com/sxpert/hp-saturn
synced 2024-09-28 15:20:27 +02:00
implement more instructions
This commit is contained in:
Raphael Jacquot
parent
94ab98a175
commit
4b7e59fa21
8 changed files with 194 additions and 73 deletions
12
README
12
README
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@ -17,4 +17,14 @@ phase_1: ________________________| |_____________________________
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_________
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phase_2: __________________________________| |___________________
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_________
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phase_3: ____________________________________________| |_________
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phase_3: ____________________________________________| |_________
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notes for using the ULX3S
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Maybe linux ujprog won't find port because of insufficient priviledge. Either run ujprog as root or have udev rule:# this is for usb-serial tty device
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SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", \
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MODE="664", GROUP="dialout"
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this is for ujprog libusb access
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ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", \
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GROUP="dialout", MODE="666"
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@ -39,6 +39,7 @@
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`define ALU_OP_JMP_REL3 18
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`define ALU_OP_JMP_REL4 19
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`define ALU_OP_JMP_ABS5 20
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`define ALU_OP_CLR_MASK 21
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// registers
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@ -24,3 +24,4 @@
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2019-02-13 14:53 51 153.35MHz 16.74ns 3.40ns 273 155.47MHz 5.53ns 2.09ns
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2019-02-13 23:21 318 113.77MHz 25.44ns 13.97ns 3061 117.75MHz 9.56ns 4.08ns
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2019-02-14 09:00 353 118.23MHz 26.00ns 12.28ns 3334 119.40MHz 10.08ns 3.84ns
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2019-02-14 22:11 403 115.09Mhz 27.38ns 11.32ns 2430 111.51Mhz 12.62ns 3.57ns
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@ -1,2 +1,2 @@
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read_verilog -I. saturn-core.v
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read_verilog -I. saturn_core.v
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synth_ecp5 -top saturn_core -json saturn-core.json
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70
saturn_alu.v
70
saturn_alu.v
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@ -17,10 +17,10 @@ module saturn_alu (
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i_clk,
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i_reset,
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i_en_alu_dump,
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i_en_alu_prep,
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i_en_alu_calc,
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i_en_alu_prep,
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i_en_alu_calc,
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i_en_alu_init,
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i_en_alu_save,
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i_en_alu_save,
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i_push,
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i_pop,
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@ -101,10 +101,11 @@ reg [3:0] f_last;
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reg [3:0] p_src1;
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reg [3:0] p_src2;
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reg p_carry;
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reg [0:0] p_carry;
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reg [3:0] c_res1;
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reg [3:0] c_res2;
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reg c_carry;
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reg [0:0] c_carry;
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reg [0:0] is_zero;
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/* alu status */
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@ -159,6 +160,14 @@ initial begin
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alu_run = 0;
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alu_done = 0;
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p_src1 = 0;
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p_src2 = 0;
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p_carry = 0;
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c_res1 = 0;
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c_res2 = 0;
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c_carry = 0;
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is_zero = 0;
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// o_alu_stall_dec = 0;
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// processor registers
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PC = 0;
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@ -271,7 +280,6 @@ always @(posedge i_clk) begin
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`endif
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end
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always @(posedge i_clk) begin
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// this happens in phase 3, right after the instruction decoder (in phase 2) is finished
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if (do_alu_init) begin
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@ -330,13 +338,12 @@ always @(posedge i_clk) begin
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`endif
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end
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// setup value for src1
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case (alu_op)
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`ALU_OP_ZERO: begin end // no source required
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`ALU_OP_COPY,
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`ALU_OP_RST_BIT,
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`ALU_OP_SET_BIT,
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`ALU_OP_2CMPL,
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`ALU_OP_JMP_REL3,
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`ALU_OP_JMP_REL4,
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`ALU_OP_JMP_ABS5:
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@ -349,10 +356,16 @@ always @(posedge i_clk) begin
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`ALU_REG_D1: p_src1 <= D1[f_start*4+:4];
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`ALU_REG_P: p_src1 <= P;
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`ALU_REG_IMM: p_src1 <= i_imm_value;
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default: $display("####UNHANDLED REGISTER %0d", reg_src1);
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endcase
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default: $display("####UNHANDLED OPERATION %0d", alu_op);
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endcase
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// setup p_carry
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// $display("fs %h | fs=0 %b | cc %b | npc %b", f_start, (f_start == 0), c_carry, (f_start == 0)?1'b1:c_carry);
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case (alu_op)
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`ALU_OP_2CMPL: p_carry <= (f_start == 0)?1'b1:c_carry;
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endcase
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end
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end
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@ -380,6 +393,11 @@ always @(posedge i_clk) begin
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`ALU_OP_COPY,
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`ALU_OP_RST_BIT,
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`ALU_OP_SET_BIT: c_res1 <= p_src1;
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`ALU_OP_2CMPL: begin
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c_carry <= (~p_src1 == 4'hf) && p_carry ;
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c_res1 <= ~p_src1 + p_carry;
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is_zero <= ((~p_src1 + p_carry) == 0) && (f_start == 0)?1:is_zero;
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end
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`ALU_OP_JMP_REL3,
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`ALU_OP_JMP_REL4,
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`ALU_OP_JMP_ABS5: jump_off[f_start*4+:4] <= p_src1;
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@ -391,6 +409,11 @@ always @(posedge i_clk) begin
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`ALU_OP_JMP_REL4: if (alu_finish)
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jump_off <= { {4{p_src1[3]}}, p_src1, jump_off[11:0] };
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endcase
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// $display("-------C- SRC1 %b %h | ~SRC1 %b %h | PC %b | RES1 %b %h | CC %b",
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// p_src1, p_src1, ~p_src1, ~p_src1, p_carry,
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// (~p_src1) + p_carry, (~p_src1) + p_carry,
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// (~p_src1) == 4'hf );
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end
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end
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@ -407,11 +430,20 @@ always @(posedge i_clk) begin
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alu_run, alu_done, o_alu_stall_dec, alu_op, f_start, f_last, jump_bse, jump_off, jump_pc, alu_finish);
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`endif
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// $display("-------S- SRC1 %b %h | ~SRC1 %b %h | PC %b | RES1 %b %h | CC %b",
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// p_src1, p_src1, ~p_src1, ~p_src1, p_carry,
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// (~p_src1) + p_carry, (~p_src1) + p_carry,
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// (~p_src1) == 4'hf );
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case (alu_op)
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`ALU_OP_ZERO,
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`ALU_OP_COPY:
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`ALU_OP_COPY,
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`ALU_OP_2CMPL:
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case (reg_dest)
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`ALU_REG_A: A [f_start*4+:4] <= c_res1;
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`ALU_REG_B: B [f_start*4+:4] <= c_res1;
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`ALU_REG_C: C [f_start*4+:4] <= c_res1;
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`ALU_REG_D: D [f_start*4+:4] <= c_res1;
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`ALU_REG_D0: D0[f_start*4+:4] <= c_res1;
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`ALU_REG_D1: D1[f_start*4+:4] <= c_res1;
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`ALU_REG_ST: ST[f_start*4+:4] <= c_res1;
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@ -426,11 +458,21 @@ always @(posedge i_clk) begin
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endcase
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endcase
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case (alu_op)
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`ALU_OP_2CMPL: CARRY <= !is_zero;
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endcase
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end
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end
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wire [19:0] next_pc;
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assign next_pc = (is_alu_op_jump && alu_finish)?jump_pc:PC + 1;
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wire [0:0] update_pc;
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wire [0:0] push_pc;
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assign next_pc = (is_alu_op_jump && alu_finish)?jump_pc:PC + 1;
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assign update_pc = !o_alu_stall_dec || is_alu_op_jump;
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assign push_pc = update_pc && i_push && alu_done;
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always @(posedge i_clk) begin
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if (i_reset)
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PC <= ~0;
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@ -454,9 +496,15 @@ always @(posedge i_clk) begin
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$display("ALU_PC 3: !stl %b | nx %5h | jmp %b | push %b",
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!o_alu_stall_dec, next_pc, is_alu_op_jump, i_push);
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`endif
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if (!o_alu_stall_dec || is_alu_op_jump) begin
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if (update_pc) begin
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PC <= next_pc;
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end
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if (push_pc) begin
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$display("PUSH PC %5h to RSTK[%0d]", PC, rstk_ptr);
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RSTK[rstk_ptr] <= PC;
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rstk_ptr <= rstk_ptr + 1;
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end
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end
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end
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@ -251,8 +251,12 @@ always @(posedge clk) begin
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en_inst_exec <= clk_phase[1:0] == 3;
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cycle_ctr <= cycle_ctr + { {31{1'b0}}, (clk_phase[1:0] == 0) };
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// stop after 50 clocks
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if (cycle_ctr == (max_cycle + 1))
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if (cycle_ctr == (max_cycle + 1)) begin
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$display(".-------------------.");
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$display("| OUT OF CYCLES |");
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$display("`-------------------´");
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clock_end <= 1;
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end
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end else begin
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clk_phase <= ~0;
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en_alu_dump <= 0;
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@ -267,7 +271,7 @@ always @(posedge clk) begin
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en_inst_exec <= 0;
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clock_end <= 0;
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cycle_ctr <= ~0;
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max_cycle <= 40;
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max_cycle <= 100;
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`ifndef SIM
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led[7:0] <= reg_pc[7:0];
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`endif
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169
saturn_decoder.v
169
saturn_decoder.v
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@ -46,6 +46,7 @@ module saturn_decoder(
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o_set_xm,
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o_set_carry,
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o_en_intr,
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o_test_carry,
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o_carry_val,
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o_ins_set_mode,
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o_mode_dec,
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@ -101,6 +102,7 @@ output reg o_direction;
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output reg o_ins_rtn;
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output reg o_set_xm;
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output reg o_set_carry;
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output reg o_test_carry;
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output reg o_carry_val;
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output reg o_en_intr;
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@ -124,7 +126,7 @@ output reg [4:0] o_mem_pos;
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* state registers
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*/
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reg [31:0] instr_ctr;
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reg [31:0] inst_counter;
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reg [0:0] next_nibble;
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reg [4:0] inst_cycles;
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@ -190,7 +192,7 @@ always @(posedge i_clk) begin
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*/
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`ifdef SIM
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if (o_ins_decoded) begin
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$write("DBG 0: ");
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$write("DBG[%5d]: ", inst_counter);
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$write("%5h ", o_ins_addr);
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// $write("[%2d] ", o_dbg_nb_nbls);
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@ -205,10 +207,9 @@ always @(posedge i_clk) begin
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$write("RT%s", o_en_intr?"I":"N");
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if (o_set_xm) $write("SXM");
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if (o_set_carry) $write("%sC", o_carry_val?"S":"C");
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$display("");
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end
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if (o_ins_set_mode) begin
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$display("SET%s", o_mode_dec?"DEC":"HEX");
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$write("SET%s", o_mode_dec?"DEC":"HEX");
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end
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if (o_ins_alu_op) begin
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@ -254,6 +255,7 @@ always @(posedge i_clk) begin
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`ALU_OP_RST_BIT,
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`ALU_OP_SET_BIT: if (!is_lc_hex)
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$write("=");
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`ALU_OP_2CMPL: $write("=-");
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`ALU_OP_EXCH,
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`ALU_OP_JMP_REL3,
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`ALU_OP_JMP_REL4,
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@ -269,7 +271,8 @@ always @(posedge i_clk) begin
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`ALU_OP_INC,
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`ALU_OP_DEC,
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`ALU_OP_ADD,
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`ALU_OP_SUB:
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`ALU_OP_SUB,
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`ALU_OP_2CMPL:
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case (o_reg_src1)
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`ALU_REG_A: $write("A");
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`ALU_REG_B: $write("B");
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@ -336,6 +339,7 @@ always @(posedge i_clk) begin
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// (o_reg_dest == `ALU_REG_P) || (o_reg_src1 == `ALU_REG_P ))) begin
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$write("\t");
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if (o_field_valid) begin
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// $write("[FT%d]", o_fields_table);
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if (o_fields_table != `FT_TABLE_value)
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case (o_field)
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@ -350,24 +354,26 @@ always @(posedge i_clk) begin
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`FT_FIELD_A: $write("A");
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endcase
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else $write("%0d", o_field_last+1);
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end else begin
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// $write("@%b@", is_load_imm);
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if (is_load_imm) begin
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if (is_p_eq) $write("%0d", o_imm_value);
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else
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for(nibble_pos=(o_mem_pos - 1); nibble_pos!=31; nibble_pos=nibble_pos-1)
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$write("%h", o_mem_load[nibble_pos*4+:4]);
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end
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else
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case (o_reg_dest)
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`ALU_REG_P,
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`ALU_REG_ST: begin end
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`ALU_REG_C:
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if (o_reg_src1 == `ALU_REG_P)
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$write("%0d", o_field_start);
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default: $write("[%h:%h]", o_field_start, o_field_last);
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endcase
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end
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// $write("@%b@", is_load_imm);
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if (is_load_imm) begin
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if (is_p_eq) $write("%0d", o_imm_value);
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else
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for(nibble_pos=(o_mem_pos - 1); nibble_pos!=31; nibble_pos=nibble_pos-1)
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$write("%h", o_mem_load[nibble_pos*4+:4]);
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end
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else
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case (o_reg_dest)
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`ALU_REG_P,
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`ALU_REG_ST: begin end
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default: $write("[%h:%h]", o_field_start, o_field_last);
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endcase
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$display("\t(%0d cycles)", inst_cycles);
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end
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$display("\t(%0d cycles)", inst_cycles);
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end
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// $display("new [%5h]--------------------------------------------------------------------", new_pc);
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`endif
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@ -400,6 +406,8 @@ reg block_jmp2_cry_clr;
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reg block_8x;
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reg block_80x;
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reg block_80Cx;
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reg block_82x;
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reg block_Fx;
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@ -432,12 +440,11 @@ wire do_block_mem_transfer;
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wire do_block_pointer_arith_const;
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wire do_block_load_p;
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wire do_block_load_c_hex;
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wire do_block_jmp2_cry_set;
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wire do_block_jmp2_cry_clr;
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wire do_block_8x;
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wire do_block_80x;
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wire do_block_80Cx;
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wire do_block_82x;
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wire do_block_Fx;
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assign do_block_0x = do_on_other_nibbles && block_0x;
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@ -455,11 +462,11 @@ assign do_block_mem_transfer = do_on_other_nibbles && block_mem_transfer;
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assign do_block_pointer_arith_const = do_on_other_nibbles && block_pointer_arith_const;
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assign do_block_load_p = do_on_other_nibbles && block_load_p;
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assign do_block_load_c_hex = do_on_other_nibbles && block_load_c_hex;
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assign do_block_jmp2_cry_set = do_on_other_nibbles && block_jmp2_cry_set;
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assign do_block_jmp2_cry_clr = do_on_other_nibbles && block_jmp2_cry_clr;
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assign do_block_8x = do_on_other_nibbles && block_8x;
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assign do_block_80x = do_on_other_nibbles && block_80x;
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assign do_block_80Cx = do_on_other_nibbles && block_80Cx;
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assign do_block_82x = do_on_other_nibbles && block_82x;
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assign do_block_Fx = do_on_other_nibbles && block_Fx;
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@ -497,6 +504,7 @@ assign dbg_write_pos = (!next_nibble?0:o_dbg_nb_nbls);
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always @(posedge i_clk) begin
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if (i_reset) begin
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inst_cycles <= 0;
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inst_counter <= 0;
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next_nibble <= 0;
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use_fields_tbl <= 0;
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o_inc_pc <= 1;
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@ -530,6 +538,7 @@ always @(posedge i_clk) begin
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* cleanup
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||||
*/
|
||||
if (do_on_first_nibble) begin
|
||||
inst_counter <= inst_counter + 1;
|
||||
inst_cycles <= 1;
|
||||
next_nibble <= 1;
|
||||
use_fields_tbl <= 0;
|
||||
|
|
@ -555,12 +564,11 @@ always @(posedge i_clk) begin
|
|||
block_pointer_arith_const <= 0;
|
||||
block_load_p <= 0;
|
||||
block_load_c_hex <= 0;
|
||||
block_jmp2_cry_set <= 0;
|
||||
block_jmp2_cry_clr <= 0;
|
||||
|
||||
|
||||
block_8x <= 0;
|
||||
block_80x <= 0;
|
||||
|
||||
block_80Cx <= 0;
|
||||
block_82x <= 0;
|
||||
block_Fx <= 0;
|
||||
|
||||
// decoder subroutine states
|
||||
|
|
@ -605,13 +613,26 @@ always @(posedge i_clk) begin
|
|||
4'h1: block_1x <= 1;
|
||||
4'h2: block_load_p <= 1;
|
||||
4'h3: block_load_c_hex <= 1;
|
||||
4'h4: block_jmp2_cry_set <= 1;
|
||||
4'h5: block_jmp2_cry_clr <= 1;
|
||||
4'h6: begin
|
||||
4'h4, 4'h5: begin
|
||||
// 400 RTNC
|
||||
// 420 NOP3
|
||||
// 4xy GOC
|
||||
// 500 RTNNC
|
||||
// 5xy GONC
|
||||
o_alu_no_stall <= 1;
|
||||
o_alu_op <= `ALU_OP_JMP_REL2;
|
||||
mem_load_max <= 1;
|
||||
o_mem_pos <= 0;
|
||||
o_test_carry <= 1;
|
||||
o_carry_val <= !i_nibble[0];
|
||||
block_jmp <= 1;
|
||||
end
|
||||
4'h6, 4'h7: begin
|
||||
o_alu_no_stall <= 1;
|
||||
o_alu_op <= `ALU_OP_JMP_REL3;
|
||||
mem_load_max <= 2;
|
||||
o_mem_pos <= 0;
|
||||
o_mem_pos <= 0;
|
||||
o_push <= i_nibble[0];
|
||||
block_jmp <= 1;
|
||||
end
|
||||
4'h8: block_8x <= 1;
|
||||
|
|
@ -810,16 +831,14 @@ always @(posedge i_clk) begin
|
|||
block_load_c_hex <= 0;
|
||||
end
|
||||
|
||||
if (do_block_jmp2_cry_clr) begin
|
||||
|
||||
end
|
||||
|
||||
|
||||
if (do_block_8x) begin
|
||||
$display("block_8x %h | op %d", i_nibble, o_alu_op);
|
||||
case (i_nibble)
|
||||
4'h0: //
|
||||
block_80x <= 1;
|
||||
4'h2:
|
||||
block_82x <= 1;
|
||||
4'h4, 4'h5: // ST=[01] n
|
||||
begin
|
||||
o_alu_op <= i_nibble[0]?`ALU_OP_SET_BIT:`ALU_OP_RST_BIT;
|
||||
|
|
@ -837,7 +856,7 @@ always @(posedge i_clk) begin
|
|||
o_mem_pos <= 0;
|
||||
block_jmp <= 1;
|
||||
// debug for cases not tested
|
||||
o_alu_debug <= i_nibble[1] || !i_nibble[0];
|
||||
o_alu_debug <= !i_nibble[0];
|
||||
end
|
||||
default: begin
|
||||
$display("block_8x %h error", i_nibble);
|
||||
|
|
@ -850,13 +869,11 @@ always @(posedge i_clk) begin
|
|||
if (do_block_80x) begin
|
||||
$display("block_80x %h | op %d", i_nibble, o_alu_op);
|
||||
case (i_nibble)
|
||||
4'hC: // C=P n
|
||||
begin
|
||||
o_ins_alu_op <= 1;
|
||||
o_alu_op <= `ALU_OP_COPY;
|
||||
next_nibble <= 0;
|
||||
o_ins_decoded <= 1;
|
||||
4'hA: begin // RESET
|
||||
next_nibble <= 0;
|
||||
o_ins_decoded <= 1;
|
||||
end
|
||||
4'hC: block_80Cx <= 1;
|
||||
default: begin
|
||||
$display("block_80x %h error", i_nibble);
|
||||
o_dec_error <= 1;
|
||||
|
|
@ -865,10 +882,38 @@ always @(posedge i_clk) begin
|
|||
block_80x <= 0;
|
||||
end
|
||||
|
||||
if (do_block_80Cx) begin
|
||||
o_ins_alu_op <= 1;
|
||||
o_alu_op <= `ALU_OP_COPY;
|
||||
next_nibble <= 0;
|
||||
o_ins_decoded <= 1;
|
||||
end
|
||||
|
||||
// 821 XM=0
|
||||
// 822 SB=0
|
||||
// 824 SR=0
|
||||
// 828 MP=0
|
||||
// 82F CLRHST
|
||||
// 82x CLRHST x
|
||||
if (do_block_82x) begin
|
||||
o_ins_alu_op <= 1;
|
||||
o_alu_op <= `ALU_OP_CLR_MASK;
|
||||
next_nibble <= 0;
|
||||
o_ins_decoded <= 1;
|
||||
end
|
||||
|
||||
|
||||
if (do_block_Fx) begin
|
||||
$display("block_Fx %h | op %d", i_nibble, o_alu_op);
|
||||
case (i_nibble)
|
||||
4'h8, 4'h9, 4'hA, 4'hB: // r=-r A
|
||||
begin
|
||||
o_fields_table <= `FT_TABLE_f;
|
||||
//o_alu_debug <= 1;
|
||||
o_ins_alu_op <= 1;
|
||||
o_alu_op <= `ALU_OP_2CMPL;
|
||||
next_nibble <= 0;
|
||||
o_ins_decoded <= 1;
|
||||
end
|
||||
default: begin
|
||||
$display("block_Fx %h error", i_nibble);
|
||||
o_dec_error <= 1;
|
||||
|
|
@ -1076,17 +1121,22 @@ always @(posedge i_clk) begin
|
|||
endcase
|
||||
end
|
||||
|
||||
if (do_block_80x) begin
|
||||
if (do_block_80Cx) begin
|
||||
o_reg_dest <= `ALU_REG_C;
|
||||
o_reg_src1 <= `ALU_REG_P;
|
||||
o_reg_src2 <= 0;
|
||||
end
|
||||
|
||||
if (do_block_Fx) begin
|
||||
case (i_nibble)
|
||||
4'hC: begin
|
||||
o_reg_dest <= `ALU_REG_C;
|
||||
o_reg_src1 <= `ALU_REG_P;
|
||||
o_reg_src2 <= 0;
|
||||
4'h8, 4'h9, 4'hA, 4'hB: begin
|
||||
o_reg_dest <= reg_ABCD;
|
||||
o_reg_src1 <= reg_ABCD;
|
||||
o_reg_src2 <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -1240,11 +1290,18 @@ always @(posedge i_clk) begin
|
|||
endcase
|
||||
end
|
||||
|
||||
if (do_block_80x) begin
|
||||
if (do_block_80Cx) begin
|
||||
o_field_start <= i_nibble;
|
||||
o_field_last <= i_nibble;
|
||||
end
|
||||
|
||||
if (do_block_Fx) begin
|
||||
case (i_nibble)
|
||||
4'hC: begin
|
||||
o_field_start <= i_nibble;
|
||||
o_field_last <= i_nibble;
|
||||
4'h8, 4'h9, 4'hA, 4'hB: begin
|
||||
o_field <= `FT_FIELD_A;
|
||||
o_field_start <= 0;
|
||||
o_field_last <= 4;
|
||||
o_field_valid <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
3 F 0 1 2 3 4 5 6 7 8 9 A B C D E F
|
||||
6 3 2 7 // NOP3
|
||||
3 4 1 0 0 0 0
|
||||
F A // NOP3
|
||||
Loading…
Reference in a new issue