mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-20 10:26:31 +01:00
implement the pieces to replicate the bus data transfers for writing data out.
This commit is contained in:
Raphael Jacquot
parent
128921c364
commit
8fc7cde507
5 changed files with 244 additions and 80 deletions
171
saturn_alu.v
171
saturn_alu.v
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@ -16,6 +16,7 @@
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module saturn_alu (
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i_clk,
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i_reset,
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i_cycle_ctr,
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i_en_alu_dump,
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i_en_alu_prep,
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i_en_alu_calc,
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@ -26,6 +27,8 @@ module saturn_alu (
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o_bus_address,
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o_bus_load_pc,
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o_bus_load_dp,
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o_bus_read_pc,
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o_bus_write_dp,
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o_bus_nibble_out,
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i_push,
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@ -61,6 +64,7 @@ module saturn_alu (
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_en_alu_dump;
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input wire [0:0] i_en_alu_prep;
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input wire [0:0] i_en_alu_calc;
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@ -71,6 +75,8 @@ input wire [0:0] i_stalled;
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output reg [19:0] o_bus_address;
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output reg [0:0] o_bus_load_pc;
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output reg [0:0] o_bus_load_dp;
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output reg [0:0] o_bus_read_pc;
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output reg [0:0] o_bus_write_dp;
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output reg [3:0] o_bus_nibble_out;
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input wire [0:0] i_push;
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@ -261,7 +267,7 @@ wire do_alu_pc;
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wire do_alu_mode;
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assign do_busclean = alu_active && i_en_alu_dump;
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assign do_alu_init = alu_active && i_en_alu_init && i_ins_alu_op && !alu_run;
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assign do_alu_init = alu_active && i_en_alu_init && i_ins_alu_op && !alu_run && !write_done;
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assign do_alu_prep = alu_active && i_en_alu_prep && alu_run;
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assign do_alu_calc = alu_active && i_en_alu_calc && alu_run;
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assign do_alu_save = alu_active && i_en_alu_save && alu_run;
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@ -277,7 +283,9 @@ assign do_go_prep = alu_active && i_en_alu_prep && i_ins_test_go;
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// the decoder may request the ALU to not stall it
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assign o_alu_stall_dec = alu_run && (!i_alu_no_stall || alu_finish || alu_go_test);
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assign o_alu_stall_dec = (!no_extra_cycles) ||
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(alu_run &&
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(!i_alu_no_stall || alu_finish || alu_go_test));
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wire alu_start;
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wire alu_finish;
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@ -309,9 +317,9 @@ assign is_alu_op_test = ((alu_op == `ALU_OP_TEST_EQ) ||
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always @(posedge i_clk) begin
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`ifdef SIM
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if (i_stalled && i_en_alu_dump)
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$display("ALU STALLED");
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`endif
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// if (i_stalled && i_en_alu_dump)
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// $display("ALU STALLED");
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// `endif
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`ifdef ALU_DEBUG_DBG
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$display("iad %b | AD %b | ad %b | ADD %b | add %b | ADJ %b | adj %b | ADP %b | adp %b",
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@ -376,18 +384,6 @@ always @(posedge i_clk) begin
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reg_src2 <= i_reg_src2;
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f_last <= i_field_last;
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if (is_mem_xfer) begin
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`ifdef SIM
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$display("ALU_XFER 3: read %b | write %b | mem_reg DAT%b",
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is_mem_read, is_mem_write, mem_reg[0]);
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$display(".------------------------------------.");
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$display("| SHOULD TELL THE BUS CONTROLLER TO |");
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$display("| LOAD D0 OR D1 INTO MODULES' DP REG |");
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$display("`------------------------------------´");
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`endif
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// DO SOMETHING TO GET THE BUS CONTROLLER TO SEND OUT
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// THE CONTENTS OF D0 OR D1 AS THE DP
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end
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end
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end
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@ -398,6 +394,7 @@ end
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always @(posedge i_clk) begin
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if (do_alu_init) begin
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$display("------------------------------------------------- DO_ALU_INIT");
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alu_run <= 1;
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f_first <= i_field_start;
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f_cur <= i_field_start;
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@ -552,7 +549,7 @@ always @(posedge i_clk) begin
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if (do_alu_calc) begin
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`ifdef SIM
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if (alu_debug)
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$display("ALU_CALC 2: run %b | done %b | stall %b | op %d | f %h | c %h | l %h | dest %d | src1 %h | src2 %h | p_carry %b",
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$display("ALU_CALC 2: run %b | done %b | stall %b | op %d | f %h | c %h | l %h | dest %d | psrc1 %h | psrc2 %h | p_carry %b",
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alu_run, alu_done, o_alu_stall_dec, alu_op, f_first, f_cur, f_last, reg_dest, p_src1, p_src2, p_carry);
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if (alu_debug_jump)
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$display("ALU_JUMP 2: run %b | done %b | stall %b | op %d | f %h | c %h | l %h | jbs %5h | jof %5h | jpc %5h | fin %b",
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@ -650,15 +647,18 @@ always @(posedge i_clk) begin
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`ALU_OP_ADD,
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`ALU_OP_CLR_MASK:
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case (reg_dest)
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`ALU_REG_A: A[f_cur*4+:4] <= c_res1;
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`ALU_REG_B: B[f_cur*4+:4] <= c_res1;
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`ALU_REG_C: C[f_cur*4+:4] <= c_res1;
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`ALU_REG_D: D[f_cur*4+:4] <= c_res1;
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`ALU_REG_D0: D0[f_cur*4+:4] <= c_res1;
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`ALU_REG_D1: D1[f_cur*4+:4] <= c_res1;
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`ALU_REG_ST: ST[f_cur*4+:4] <= c_res1;
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`ALU_REG_P: P <= c_res1;
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`ALU_REG_HST: HST <= c_res1;
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`ALU_REG_A: A[f_cur*4+:4] <= c_res1;
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`ALU_REG_B: B[f_cur*4+:4] <= c_res1;
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`ALU_REG_C: C[f_cur*4+:4] <= c_res1;
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`ALU_REG_D: D[f_cur*4+:4] <= c_res1;
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`ALU_REG_D0: D0[f_cur*4+:4] <= c_res1;
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`ALU_REG_D1: D1[f_cur*4+:4] <= c_res1;
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`ALU_REG_ST: ST[f_cur*4+:4] <= c_res1;
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`ALU_REG_P: P <= c_res1;
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`ALU_REG_DAT0,
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`ALU_REG_DAT1: o_bus_nibble_out <= c_res1;
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`ALU_REG_HST: HST <= c_res1;
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default: $display("#### ALU_SAVE invalid register %0d for op %0d", reg_dest, alu_op);
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endcase
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`ALU_OP_RST_BIT,
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`ALU_OP_SET_BIT:
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@ -733,6 +733,11 @@ wire [0:0] pop_pc;
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wire [0:0] reload_pc;
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wire [0:0] push_pc;
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reg [1:0] extra_cycles;
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wire [0:0] no_extra_cycles;
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wire [1:0] cycles_to_go;
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reg [0:0] write_done;
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assign next_pc = (is_alu_op_jump && alu_finish)?jump_pc:PC + 1;
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assign goyes_off = {{12{i_imm_value[3]}}, i_imm_value, jump_off[3:0]};
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assign goyes_pc = jump_bse + goyes_off;
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@ -745,10 +750,17 @@ assign pop_pc = i_pop && i_ins_rtn &&
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assign reload_pc = uncond_jmp || pop_pc || just_reset;
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assign push_pc = update_pc && i_push && alu_finish;
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assign no_extra_cycles = (extra_cycles == 0);
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assign cycles_to_go = extra_cycles - 1;
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always @(posedge i_clk) begin
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if (i_reset) begin
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PC <= ~0;
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just_reset <= 1;
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PC <= ~0;
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just_reset <= 1;
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extra_cycles <= 0;
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o_bus_load_pc <= 0;
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o_bus_load_dp <= 0;
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o_bus_write_dp <= 0;
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end
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@ -766,8 +778,74 @@ always @(posedge i_clk) begin
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`endif
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/*
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* updates the PC
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*
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* Request the D0 or D1 pointers to be loaded to other
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* modules through the bus
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*
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*/
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// $display("[!no_ec %b] || ( [run %b] && ( [!nstll %b] || [fin %b] || [test %b] ))",
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// !no_extra_cycles, alu_run, !i_alu_no_stall, alu_finish, alu_go_test);
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if (do_alu_init) begin
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if (is_mem_xfer && !write_done) begin
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`ifdef SIM
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$display("ALU_XFER 3: read %b | write %b | mem_reg DAT%b",
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is_mem_read, is_mem_write, mem_reg[0]);
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// $display(".------------------------------------.");
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// $display("| SHOULD TELL THE BUS CONTROLLER TO |");
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// $display("| LOAD D0 OR D1 INTO MODULES' DP REG |");
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// $display("`------------------------------------´");
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`endif
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// DO SOMETHING TO GET THE BUS CONTROLLER TO SEND OUT
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// THE CONTENTS OF D0 OR D1 AS THE DP
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case (mem_reg[0])
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0: o_bus_address <= D0;
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1: o_bus_address <= D1;
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endcase
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o_bus_load_dp <= 1;
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end
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end
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if (do_busclean && alu_run && !write_done)
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if (is_mem_write && !o_bus_write_dp) begin
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// $display("ALUWRITE %0d: [%d] setting up write", `PH_ALU_DUMP, i_cycle_ctr);
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o_bus_write_dp <= 1;
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end
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// writing needs one more cycle as the DP_WRITE command
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// needs to be send
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if (do_alu_save && alu_finish && is_mem_write && (extra_cycles == 0)) begin
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// $display("ALUWRITE %0d: [%d] 2 EXTRA CYCLES", `PH_ALU_SAVE, i_cycle_ctr);
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extra_cycles <= 2;
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write_done <= 1;
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end
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if (i_en_alu_calc && !no_extra_cycles) begin
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// $display("ALUWRITE %0d: [%d] %0d CYCLES TO GO", `PH_ALU_SAVE, i_cycle_ctr, cycles_to_go);
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extra_cycles <= cycles_to_go;
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if (cycles_to_go == 1) begin
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o_bus_write_dp <= 0;
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o_bus_read_pc <= 1;
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end
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end
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if (i_en_alu_dump && no_extra_cycles && o_bus_read_pc) begin
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// $display("ALUWRITE %0d: [%d] RELEASE DECODER", `PH_ALU_DUMP, i_cycle_ctr);
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o_bus_read_pc <= 0;
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write_done <= 0;
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end
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/**
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*
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* Update the PC.
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* Request the new PC be loaded to the other modules through
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* the bus if necessary
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*
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*/
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if (do_alu_pc) begin
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// $display("DO ALU PC");
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`ifdef SIM
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@ -778,19 +856,20 @@ always @(posedge i_clk) begin
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!o_alu_stall_dec, next_pc, alu_done, alu_finish,
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is_alu_op_jump, i_ins_rtn, i_push,
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i_imm_value, jump_bse, goyes_off, goyes_pc);
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if (reload_pc) begin
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$display(".---------------------------------.");
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$display("| SHOULD TELL THE BUS CONTROLLER |");
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$display("| TO LOAD PC INTO MODULES' PC REG |");
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$display("`---------------------------------´");
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end
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// if (reload_pc) begin
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// $display(".---------------------------------.");
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// $display("| SHOULD TELL THE BUS CONTROLLER |");
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// $display("| TO LOAD PC INTO MODULES' PC REG |");
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// $display("`---------------------------------´");
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// end
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`endif
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// if we just came out of reset, simulate a long jump to 0
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if (just_reset) begin
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$display("ALU_RSET 3: simulating GOVLNG to PC");
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// $display("ALU_RSET 3: simulating GOVLNG to PC");
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// cancel this signal for good once reset is gone
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just_reset <= 0;
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just_reset <= 0;
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o_bus_read_pc <= 1;
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end
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// this may do wierd things with C=RSTK...
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@ -799,7 +878,7 @@ always @(posedge i_clk) begin
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end
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if (reload_pc) begin
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$display("ALU_PC 3: $$$$ RELOADING PC $$$$");
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// $display("ALU_PC 3: $$$$ RELOADING PC $$$$");
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o_bus_address <= pop_pc ? RSTK[rstk_ptr-1] : next_pc;
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o_bus_load_pc <= 1;
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end
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@ -819,9 +898,17 @@ always @(posedge i_clk) begin
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end
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end
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// deactivate o_load_pc
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if (do_busclean && o_bus_load_pc)
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o_bus_load_pc <= 0;
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/*
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*
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* Deactivate the load_pc or load_dp enables on the next clock
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*
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*/
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if (do_busclean && (o_bus_load_pc || o_bus_load_dp)) begin
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$display("BUSCLEAN %0d: cleaning the various bus control bits", `PH_ALU_DUMP);
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o_bus_load_pc <= 0;
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o_bus_load_dp <= 0;
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end
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end
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@ -28,6 +28,8 @@ module saturn_bus_ctrl (
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i_address,
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i_load_pc,
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i_load_dp,
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i_read_pc,
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i_write_dp,
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i_nibble,
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o_nibble
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);
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@ -52,6 +54,8 @@ input wire [19:0] i_alu_pc;
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input wire [19:0] i_address;
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input wire [0:0] i_load_pc;
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input wire [0:0] i_load_dp;
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input wire [0:0] i_read_pc;
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input wire [0:0] i_write_dp;
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input wire [3:0] i_nibble;
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output reg [3:0] o_nibble;
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@ -84,21 +88,23 @@ initial begin
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// $readmemh( "testrom-2.hex", rom);
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// $monitor("addr %5h | strb %b | c/d %b | cnt %0d | odata %h | idata %h",
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// i_address, o_bus_strobe, o_bus_cmd_data, addr_cnt, o_bus_data, i_bus_data);
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// $monitor("MONITOR : strb %b | o_bus_data %h | i_bus_data %h", o_bus_strobe, o_bus_data, i_bus_data);
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`endif
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end
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reg [2:0] addr_cnt;
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reg [0:0] send_addr;
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reg [3:0] last_cmd;
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reg [2:0] addr_cnt;
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reg [0:0] send_addr;
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reg [19:0] local_pc;
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reg [19:0] local_dp;
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always @(posedge i_clk) begin
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if (i_reset) begin
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o_stalled_by_bus <= 0;
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o_bus_strobe <= 0;
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o_bus_cmd_data <= 1; // 1 is the default level
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addr_cnt <= 0;
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addr_cnt <= 0;
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end
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/*
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@ -108,35 +114,90 @@ always @(posedge i_clk) begin
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*/
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if (en_bus_send) begin
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/*
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* Sending LOAD_PC or LOAD_DP
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*/
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if (i_load_pc) begin
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$display("BUS_SEND %0d: loading pc %h", `PH_BUS_SEND, i_address);
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$display("BUS_SEND %0d: [%d] LOAD_PC %h", `PH_BUS_SEND, i_cycle_ctr, i_address);
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o_bus_data <= `BUSCMD_LOAD_PC;
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last_cmd <= `BUSCMD_LOAD_PC;
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end
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if (i_load_dp) begin
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$display("BUS_SEND %0d: loading dp %h", `PH_BUS_SEND, i_address);
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$display("BUS_SEND %0d: [%d] LOAD_DP %h", `PH_BUS_SEND, i_cycle_ctr, i_address);
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o_bus_data <= `BUSCMD_LOAD_DP;
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last_cmd <= `BUSCMD_LOAD_DP;
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end
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if (i_load_pc || i_load_dp) begin
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o_stalled_by_bus <= 1;
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o_bus_cmd_data <= 0;
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addr_cnt <= 0;
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send_addr <= 1;
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o_bus_cmd_data <= 0;
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addr_cnt <= 0;
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send_addr <= 1;
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o_bus_strobe <= 1;
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end
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// sending address bits
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if (send_addr) begin
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$display("BUS_SEND %0d: send addr nibble %0d [%h]", `PH_BUS_SEND, addr_cnt, i_address[addr_cnt*4+:4]);
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$display("BUS_SEND %0d: [%d] addr[%0d] %h =>",
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`PH_BUS_SEND, i_cycle_ctr, addr_cnt, i_address[addr_cnt*4+:4]);
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o_bus_data <= i_address[addr_cnt*4+:4];
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addr_cnt <= addr_cnt + 1;
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o_bus_strobe <= 1;
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||||
end
|
||||
|
||||
if (!i_read_stall || send_addr)
|
||||
/*
|
||||
* send the PC_READ command to restore the instruction flow
|
||||
* after a data transfer
|
||||
*/
|
||||
|
||||
if (i_read_pc) begin
|
||||
if (last_cmd != `BUSCMD_PC_READ) begin
|
||||
$display("BUS_SEND %0d: [%d] PC_READ", `PH_BUS_SEND, i_cycle_ctr);
|
||||
o_bus_data <= `BUSCMD_PC_READ;
|
||||
last_cmd <= `BUSCMD_PC_READ;
|
||||
end
|
||||
o_bus_strobe <= 1;
|
||||
end
|
||||
|
||||
if ((last_cmd == `BUSCMD_PC_READ) && !i_read_stall)
|
||||
o_bus_strobe <= 1;
|
||||
|
||||
/*
|
||||
* writing data to the bus,
|
||||
* send DP_WRITE first if necessary
|
||||
*/
|
||||
|
||||
if (i_write_dp && (addr_cnt == 5)) begin
|
||||
if (last_cmd != `BUSCMD_DP_WRITE) begin
|
||||
$display("BUS_SEND %0d: [%d] DP_WRITE", `PH_BUS_SEND, i_cycle_ctr);
|
||||
o_bus_data <= `BUSCMD_DP_WRITE;
|
||||
last_cmd <= `BUSCMD_DP_WRITE;
|
||||
o_bus_strobe <= 1;
|
||||
end else begin
|
||||
$display("BUS_SEND %0d: [%d] WRITE %h =>", `PH_BUS_SEND, i_cycle_ctr, i_nibble);
|
||||
o_bus_data <= i_nibble;
|
||||
o_bus_strobe <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
|
||||
if (en_bus_ecmd && send_addr && (addr_cnt == 5)) begin
|
||||
$display("BUS_ECMD %0d: releasing stall after sending addr", `PH_BUS_ECMD);
|
||||
case (last_cmd)
|
||||
`BUSCMD_LOAD_PC: begin
|
||||
$display("BUS_ECMD %0d: [%d] <= PC_READ mode", `PH_BUS_ECMD, i_cycle_ctr);
|
||||
last_cmd <= `BUSCMD_PC_READ;
|
||||
local_pc <= i_address;
|
||||
end
|
||||
`BUSCMD_LOAD_DP: begin
|
||||
$display("BUS_ECMD %0d: [%d] <= DP_READ mode", `PH_BUS_ECMD, i_cycle_ctr);
|
||||
last_cmd <= `BUSCMD_DP_READ;
|
||||
local_dp <= i_address;
|
||||
end
|
||||
endcase
|
||||
send_addr <= 0;
|
||||
o_stalled_by_bus = 0;
|
||||
end
|
||||
|
|
@ -146,9 +207,15 @@ always @(posedge i_clk) begin
|
|||
* reading data from the bus
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
if (en_bus_recv && !i_read_stall) begin
|
||||
$display("BUS_RECV %0d: [%d] nibble %h", `PH_BUS_RECV, i_cycle_ctr, rom[i_alu_pc[`ROMBITS-1:0]]);
|
||||
o_nibble <= rom[i_alu_pc[`ROMBITS-1:0]];
|
||||
if (last_cmd == `BUSCMD_PC_READ) begin
|
||||
$display("BUS_RECV %0d: [%d] <= READ %h", `PH_BUS_RECV, i_cycle_ctr, rom[local_pc[`ROMBITS-1:0]]);
|
||||
o_nibble <= rom[local_pc[`ROMBITS-1:0]];
|
||||
local_pc <= local_pc + 1;
|
||||
end else
|
||||
$display("BUS_RECV %0d: [%d] UNKNOWN COMMAND %h", `PH_BUS_RECV, i_cycle_ctr, last_cmd);
|
||||
end
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -86,6 +86,7 @@ saturn_decoder m_decoder (
|
|||
.i_en_dbg (ck_debugger),
|
||||
.i_en_dec (ck_inst_dec),
|
||||
.i_pc (reg_pc),
|
||||
.i_bus_load_pc (bus_load_pc),
|
||||
.i_stalled (dec_stalled),
|
||||
.i_nibble (bus_nibble_in),
|
||||
|
||||
|
|
@ -156,6 +157,7 @@ wire [0:0] ins_test_go;
|
|||
saturn_alu m_alu (
|
||||
.i_clk (clk),
|
||||
.i_reset (reset),
|
||||
.i_cycle_ctr (cycle_ctr),
|
||||
.i_en_alu_dump (ck_alu_dump),
|
||||
.i_en_alu_prep (ck_alu_prep),
|
||||
.i_en_alu_calc (ck_alu_calc),
|
||||
|
|
@ -166,6 +168,8 @@ saturn_alu m_alu (
|
|||
.o_bus_address (bus_address),
|
||||
.o_bus_load_pc (bus_load_pc),
|
||||
.o_bus_load_dp (bus_load_dp),
|
||||
.o_bus_read_pc (bus_read_pc),
|
||||
.o_bus_write_dp (bus_write_dp),
|
||||
.o_bus_nibble_out (bus_nibble_out),
|
||||
|
||||
.i_push (push),
|
||||
|
|
@ -204,6 +208,8 @@ saturn_alu m_alu (
|
|||
wire [19:0] bus_address;
|
||||
wire [0:0] bus_load_pc;
|
||||
wire [0:0] bus_load_dp;
|
||||
wire [0:0] bus_read_pc;
|
||||
wire [0:0] bus_write_dp;
|
||||
|
||||
wire [3:0] bus_nibble_in;
|
||||
wire [3:0] bus_nibble_out;
|
||||
|
|
@ -241,6 +247,8 @@ saturn_bus_ctrl m_bus_ctrl (
|
|||
.i_address (bus_address),
|
||||
.i_load_pc (bus_load_pc),
|
||||
.i_load_dp (bus_load_dp),
|
||||
.i_read_pc (bus_read_pc),
|
||||
.i_write_dp (bus_write_dp),
|
||||
.i_nibble (bus_nibble_out),
|
||||
.o_nibble (bus_nibble_in)
|
||||
);
|
||||
|
|
@ -313,7 +321,6 @@ always @(posedge clk) begin
|
|||
ck_alu_save <= clk_phase[1:0] == `PH_ALU_SAVE;
|
||||
|
||||
cycle_ctr <= cycle_ctr + { {31{1'b0}}, (clk_phase[1:0] == `PH_BUS_SEND) };
|
||||
// stop after 50 clocks
|
||||
if (cycle_ctr == (max_cycle + 1)) begin
|
||||
$display(".-------------------.");
|
||||
$display("| OUT OF CYCLES |");
|
||||
|
|
@ -340,7 +347,7 @@ always @(posedge clk) begin
|
|||
|
||||
clock_end <= 0;
|
||||
cycle_ctr <= ~0;
|
||||
max_cycle <= 20;
|
||||
max_cycle <= 155;
|
||||
|
||||
mem_ctrl_stall <= 0;
|
||||
`ifndef SIM
|
||||
|
|
|
|||
|
|
@ -8,7 +8,8 @@
|
|||
`include "def-alu.v"
|
||||
|
||||
module saturn_decoder(
|
||||
i_clk, i_reset, i_cycles, i_en_dbg, i_en_dec, i_stalled,
|
||||
i_clk, i_reset, i_cycles, i_en_dbg, i_en_dec,
|
||||
i_bus_load_pc, i_stalled,
|
||||
i_pc, i_nibble,
|
||||
|
||||
i_reg_p,
|
||||
|
|
@ -41,26 +42,27 @@ module saturn_decoder(
|
|||
input wire [0:0] i_clk;
|
||||
input wire [0:0] i_reset;
|
||||
input wire [31:0] i_cycles;
|
||||
input wire i_en_dbg;
|
||||
input wire i_en_dec;
|
||||
input wire i_stalled;
|
||||
input wire [0:0] i_en_dbg;
|
||||
input wire [0:0] i_en_dec;
|
||||
input wire [0:0] i_bus_load_pc;
|
||||
input wire [0:0] i_stalled;
|
||||
input wire [19:0] i_pc;
|
||||
input wire [3:0] i_nibble;
|
||||
|
||||
input wire [3:0] i_reg_p;
|
||||
|
||||
output reg o_inc_pc;
|
||||
output reg o_push;
|
||||
output reg o_pop;
|
||||
output reg o_dec_error;
|
||||
output reg [0:0] o_inc_pc;
|
||||
output reg [0:0] o_push;
|
||||
output reg [0:0] o_pop;
|
||||
output reg [0:0] o_dec_error;
|
||||
`ifdef SIM
|
||||
output reg [0:0] o_unimplemented;
|
||||
`endif
|
||||
output reg o_alu_debug;
|
||||
output reg [0:0] o_alu_debug;
|
||||
|
||||
// instructions related outputs
|
||||
output reg [19:0] o_ins_addr;
|
||||
output reg o_ins_decoded;
|
||||
output reg [0:0] o_ins_decoded;
|
||||
|
||||
output reg [1:0] o_fields_table;
|
||||
output reg [3:0] o_field;
|
||||
|
|
@ -76,20 +78,20 @@ output reg [4:0] o_reg_src1;
|
|||
output reg [4:0] o_reg_src2;
|
||||
|
||||
// rtn specific
|
||||
output reg o_ins_rtn;
|
||||
output reg o_set_xm;
|
||||
output reg o_set_carry;
|
||||
output reg o_test_carry;
|
||||
output reg o_carry_val;
|
||||
output reg o_en_intr;
|
||||
output reg [0:0] o_ins_rtn;
|
||||
output reg [0:0] o_set_xm;
|
||||
output reg [0:0] o_set_carry;
|
||||
output reg [0:0] o_test_carry;
|
||||
output reg [0:0] o_carry_val;
|
||||
output reg [0:0] o_en_intr;
|
||||
|
||||
// setdec/hex
|
||||
output reg o_ins_set_mode;
|
||||
output reg o_mode_dec;
|
||||
output reg [0:0] o_ins_set_mode;
|
||||
output reg [0:0] o_mode_dec;
|
||||
|
||||
// alu_operations
|
||||
output reg o_ins_alu_op;
|
||||
output reg o_ins_test_go;
|
||||
output reg [0:0] o_ins_alu_op;
|
||||
output reg [0:0] o_ins_test_go;
|
||||
|
||||
/* data used by the debugger
|
||||
*
|
||||
|
|
@ -434,6 +436,7 @@ always @(posedge i_clk) begin
|
|||
block_13x <= 1;
|
||||
4'h4, 4'h5: // DAT[01]=[AC] <field>
|
||||
begin
|
||||
o_alu_debug <= 0;
|
||||
`ifdef SIM
|
||||
$display("block_1x %h | use table <= %b", i_nibble, i_nibble[0]);
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ wire [19:0] new_pc;
|
|||
assign new_pc = i_pc + 1;
|
||||
|
||||
wire run_debugger;
|
||||
assign run_debugger = !i_reset && i_en_dbg && !i_stalled && !next_nibble;
|
||||
assign run_debugger = !i_reset && i_en_dbg && !i_stalled && !i_bus_load_pc && !next_nibble;
|
||||
|
||||
wire is_short_transfer;
|
||||
assign is_short_transfer = (o_field_last == 3) &&
|
||||
|
|
|
|||
Loading…
Reference in a new issue