30 commits

Author	SHA1	Message	Date
Raphael Jacquot	175c1a48d0	major surgery, add memory read and write back in	2019-03-15 07:15:45 +01:00
Raphael Jacquot	a533e4ea37	cleanup the startup procedure	2019-03-14 17:52:03 +01:00
Raphael Jacquot	c62d562008	make it so that execution of bus programs happen ... in the same cycle as the instruction modify the way jump and rtn are handled add some registers to the debugger	2019-03-14 16:37:51 +01:00
Raphael Jacquot	9549b53edc	implement bus trasfers debugging	2019-03-06 18:19:02 +01:00
Raphael Jacquot	6d940c7f95	fix the conditions for the debugger to spew chars aout	2019-03-06 14:41:18 +01:00
Raphaël Jacquot	f86a1d03c5	implement base alu functionnality	2019-03-06 12:16:34 +01:00
Raphael Jacquot	f12a74a917	print a "." when the bus is active, but not reading	2019-03-05 06:47:02 +01:00
Raphaël Jacquot	28483afe9a	implement CONFIG and RTN* (0[0-3])	2019-03-05 05:39:34 +01:00
Raphael Jacquot	9168cbc1a2	victory, this works on the fpga \o/ ... using "=" instead of "<=" is evil ! make the fpga halt when necessary	2019-03-04 22:48:09 +01:00
Raphael Jacquot	4d578f8f18	ok, we're getting somewhere	2019-03-04 21:10:12 +01:00
Raphael Jacquot	6964b72df1	ok. serial sort of works, except it doesn't...	2019-03-04 18:29:00 +01:00
Raphael Jacquot	6f3f3ce73c	debug the seial port	2019-03-04 17:01:59 +01:00
Raphaël Jacquot	7708d7a85c	attached serial port tentative	2019-03-04 14:40:31 +01:00
Raphaël Jacquot	479382e004	export rstk_ptr to debugger ... implement LCHEX (and almost done for LAHEX)	2019-03-04 13:28:08 +01:00
Raphaël Jacquot	e47f12f1d7	implement push PC to RSTK	2019-03-04 11:52:05 +01:00
Raphaël Jacquot	908b96df6f	implement CLRHST and variants ... implement SET[HEX|DEC]	2019-03-04 10:53:37 +01:00
Raphaël Jacquot	8a631c28c2	fix missing bus state reset	2019-03-04 10:14:44 +01:00
Raphaël Jacquot	18a56d750b	export main registers to debugger ... add C register implement C=P n add dumping C register	2019-03-04 09:58:13 +01:00
Raphaël Jacquot	009f01f5d7	implement 8[45]x ST=[01] n ... implement GOVLNG dump 2 lines of registers in debugger now	2019-03-04 08:08:02 +01:00
Raphaël Jacquot	6dd38500a8	add a counter to slow things down	2019-03-03 15:19:07 +01:00
Raphaël Jacquot	b58be38b10	connect debugger to leds	2019-03-03 13:33:32 +01:00
Raphaël Jacquot	eeb5150159	add the beginnings of a PC and RSTK handler ... fix bad maths in the rom-gx-r module wire in the PC in the debugger and the control unit add an execute flag, to start execution of partially decoded instructions that need reading data from the instruction stream	2019-03-03 09:33:42 +01:00
Raphael Jacquot	21ad359673	fix compiling ... fix the way the bus controller program worked, which generated evil inferred latches	2019-03-02 22:33:58 +01:00
Raphaël Jacquot	2fcd9f7b23	decode our first instruction ... execute said instruction start implementing the debugging engine to see what we are doing	2019-03-02 19:40:31 +01:00
Raphael Jacquot	c5355b4a90	enough was done to start feeding the decoder	2019-03-02 15:52:56 +01:00
Raphael Jacquot	cd2b74dcc8	add some commenting	2019-03-02 15:01:00 +01:00
Raphael Jacquot	3cbd6ac5e1	we are now up to reading the first instruction nibbles	2019-03-02 14:38:01 +01:00
Raphael Jacquot	8ce2d2a993	implement more of the bus controller	2019-03-02 13:22:09 +01:00
Raphael Jacquot	e761f984c8	implement the basic rom, and add a few things	2019-02-25 09:17:17 +01:00
Raphael Jacquot	8866b8c175	starts complete rewrite	2019-02-24 23:30:57 +01:00