69 commits

Author	SHA1	Message	Date
Raphael Jacquot	c7cc7f417b	refactor as it was getting too complicated ... secret seems to limit the levels of imbricated ifs... added SETHEX SETDEC RSTK=C C=RSTK	2019-02-12 07:48:25 +01:00
Raphael Jacquot	d4c67cf8fc	finally, something that is synthesizable !	2019-02-12 00:07:12 +01:00
Raphael Jacquot	9ecdc1799b	successfully handles the first 4 opcodes and bails out on error	2019-02-11 22:57:00 +01:00
Raphael Jacquot	17c2278c99	yay, decodes the first 4 opcodes \o/	2019-02-11 22:29:13 +01:00
Raphael Jacquot	c454fb8b97	test of new decoder structure	2019-02-11 21:29:04 +01:00
Raphael Jacquot	2c06ce0359	major surgery in progress	2019-02-11 20:27:51 +01:00
Raphael Jacquot	9b2f5fa41c	more clocking work	2019-02-11 19:49:22 +01:00
Raphael Jacquot	be83ee0eed	rework the clocking	2019-02-11 19:24:57 +01:00
Raphael Jacquot	cbfbe4eb3f	renumber debug opcodes ... add add_cst and sub_cst alu opcodes port pointer math to use ALU make A[ab]x more readable	2019-02-11 15:36:51 +01:00
Raphael Jacquot	9799ea7618	use the ALU for 13x opcodes ... comment debug code add some debug code elsewhere	2019-02-11 13:17:18 +01:00
Raphael Jacquot	b39c56a43c	make things more readable	2019-02-11 11:29:31 +01:00
Raphael Jacquot	6d8924cf1d	clear alu_debug and dbg_op_code on each instruction start	2019-02-11 10:29:05 +01:00
Raphael Jacquot	046fa457be	add stuff for a future debugger	2019-02-11 09:13:16 +01:00
Raphael Jacquot	46890c6394	refactor ALU operations	2019-02-11 07:04:42 +01:00
Raphael Jacquot	d6b59740dd	add Dn=(2)	2019-02-10 23:00:20 +01:00
Raphael Jacquot	799fc3c327	convert stuff to use the ALU module instead	2019-02-10 22:02:39 +01:00
Raphael Jacquot	f21dcd8c23	add alu stuff	2019-02-10 18:46:26 +01:00
Raphael Jacquot	4e33d9c145	fix documentation comprehension error	2019-02-10 13:50:11 +01:00
Raphael Jacquot	efd93e4a95	add or substract constant do D0 and D1	2019-02-10 13:39:56 +01:00
Raphael Jacquot	bde3e1a027	add D0=(4) and transfer on field W	2019-02-10 12:47:50 +01:00
Raphael Jacquot	23a8e32e31	implement more things, test with ice40	2019-02-10 12:04:53 +01:00
Raphael Jacquot	4594dec086	more stuff implemented	2019-02-10 09:02:24 +01:00
Raphael Jacquot	71b2349831	lots of corrections	2019-02-09 19:18:58 +01:00
Raphael Jacquot	8fa16e6a1e	add more stuff	2019-02-09 11:53:45 +01:00
Raphael Jacquot	de5bfe83cc	implement loading into D1 too	2019-02-09 09:49:22 +01:00
Raphael Jacquot	8ae31087eb	bus access all rewritten	2019-02-09 09:32:29 +01:00
Raphael Jacquot	686f91f1c9	Implement reset	2019-02-09 00:01:48 +01:00
Raphael Jacquot	2d5a5d7457	implement CONFIGURE and DP_WRITE	2019-02-08 21:11:47 +01:00
Raphael Jacquot	cd185eeff0	rewrite in less spaghetti code style	2019-02-08 19:09:13 +01:00
Raphael Jacquot	92fe235e07	add an instruction counter	2019-02-08 12:46:32 +01:00
Raphael Jacquot	a56f472a45	optimize SETDEC	2019-02-08 11:55:47 +01:00
Raphael Jacquot	0f456bf0af	fix more PC handling issues	2019-02-08 11:47:06 +01:00
Raphael Jacquot	5559deab1d	fix more PC stuff	2019-02-08 11:15:16 +01:00
Raphael Jacquot	bcf79c9d7d	fix handling of PC increments and the like	2019-02-08 11:06:19 +01:00
Raphael Jacquot	90a8a4e9a9	implement more stuff	2019-02-08 00:02:55 +01:00
Raphael Jacquot	24c49893a1	implement more instructions, catch errors	2019-02-07 23:31:35 +01:00
Raphael Jacquot	55bdfed19a	entirely redesign the state machine	2019-02-07 22:54:06 +01:00
Raphael Jacquot	4800c6f241	try replacing all ifs with a case... yosys blows up too	2019-02-07 11:54:11 +01:00
Raphael Jacquot	0940b198d3	remove multiple posedge clk, which doesn't work	2019-02-07 09:38:27 +01:00
Raphael Jacquot	b5c3a56273	separate reading instructions from reading data	2019-02-07 08:35:59 +01:00
Raphael Jacquot	7a1bc5956e	add an ifdef	2019-02-07 07:11:11 +01:00
Raphael Jacquot	953323c7b8	rename runstates and starts splitting things up	2019-02-07 06:29:47 +01:00
Raphael Jacquot	3c32cbc213	attempt to fix bus	2019-02-06 17:50:36 +01:00
Raphael Jacquot	b8fa3b2df0	fix nibble_out in bus	2019-02-06 17:43:14 +01:00
Raphael Jacquot	62b1ab0292	attempt at bus are failing. what am I missing ?	2019-02-06 17:39:25 +01:00
Raphael Jacquot	b0bbacb0cc	fix bad assign types	2019-02-06 16:44:52 +01:00
Raphael Jacquot	98ff32e61c	make messages for GOTO, GOVLNG and GOSBVL better	2019-02-06 16:14:09 +01:00
Raphael Jacquot	16d9149f1a	implement the bus, with priority. currently, only rom and io_ram	2019-02-06 16:04:02 +01:00
Raphael Jacquot	c77b714777	implement some of the bus commands for the io_ram module.	2019-02-06 14:33:44 +01:00
Raphael Jacquot	82f4df8e93	add licence info	2019-02-06 10:40:55 +01:00