mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
543 lines
No EOL
12 KiB
Verilog
543 lines
No EOL
12 KiB
Verilog
/*
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* Licence: GPLv3 or later
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*/
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`default_nettype none //
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`include "bus_commands.v"
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`include "hp48_00_bus.v"
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/**************************************************************************************************
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*
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*
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*
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*
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*
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*/
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`ifdef SIM
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module saturn_core (
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input clk,
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input reset,
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output halt,
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output [3:0] busstate,
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output [11:0] decstate
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);
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`else
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module saturn_core (
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input clk_25mhz,
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input [ 6:0] btn,
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// output wifi_gpio0,
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output [7:0] led
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);
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wire clk;
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wire reset;
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reg clk2;
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// assign wifi_gpio0 = 1'b1;
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assign clk = clk_25mhz;
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assign reset = btn[1];
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`endif
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// data transfer constants
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// clocks
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reg clk2;
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reg clk3;
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wire bus_ctrl_clk;
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wire ph0;
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wire ph1;
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wire ph2;
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wire ph3;
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reg en_bus_clk;
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wire bus_strobe;
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reg en_dec_clk;
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wire dec_strobe;
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// state machine stuff
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wire halt;
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reg [31:0] cycle_ctr;
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reg [31:0] instr_ctr;
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reg decode_error;
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reg debug_stop;
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reg [3:0] cycle_type;
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reg [3:0] next_cycle;
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reg read_next_pc;
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reg execute_cycle;
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reg inc_pc;
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reg read_nibble;
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reg first_nibble;
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reg [11:0] decstate;
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reg [11:0] fields_return;
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reg [3:0] regdump;
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// bus access
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reg [19:0] bus_address;
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reg [3:0] bus_command;
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reg [3:0] bus_nibble_in;
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wire [3:0] bus_nibble_out;
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wire bus_error;
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reg bus_load_pc;
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reg en_bus_load_pc;
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// should go away, the rom should work like any other bus module
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reg [7:0] display_counter;
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// internal registers
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reg [19:0] new_PC;
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reg [19:0] next_PC;
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reg [19:0] inst_start_PC;
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reg [2:0] rstk_ptr;
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reg [19:0] jump_base;
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reg [19:0] jump_offset;
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reg hex_dec;
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`define MODE_HEX 0;
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`define MODE_DEC 1;
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// data transfer registers
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reg [3:0] t_offset;
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reg [3:0] t_cnt;
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reg [3:0] t_ctr;
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reg t_dir;
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reg t_ptr;
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reg t_reg;
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reg t_ftype;
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reg [3:0] t_field;
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reg [3:0] nb_in;
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reg [3:0] nb_out;
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reg [19:0] add_out;
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// temporary stuff
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reg t_set_test;
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reg t_set_test_val;
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reg t_add_sub;
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reg [3:0] t_first;
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reg [3:0] t_last;
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// alu control
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reg [3:0] field;
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reg [1:0] field_table;
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reg [3:0] alu_op;
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reg [3:0] alu_first;
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reg [3:0] alu_last;
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reg [3:0] alu_reg_src1;
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reg [3:0] alu_reg_src2;
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reg [3:0] alu_reg_dest;
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reg [3:0] alu_src1;
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reg [3:0] alu_src2;
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reg [3:0] alu_tmp;
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reg alu_carry;
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reg alu_debug;
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reg alu_halt;
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reg alu_requested_halt;
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reg [11:0] alu_return;
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reg [3:0] alu_next_cycle;
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// processor registers
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reg [19:0] PC;
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reg [3:0] P;
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reg [15:0] ST;
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reg [3:0] HST;
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reg Carry;
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reg [19:0] RSTK[0:7];
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reg [19:0] D0;
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reg [19:0] D1;
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reg [63:0] A;
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reg [63:0] B;
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reg [63:0] C;
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reg [63:0] D;
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reg [63:0] R0;
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reg [63:0] R1;
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reg [63:0] R2;
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reg [63:0] R3;
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reg [63:0] R4;
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hp48_bus bus_ctrl (
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.strobe (bus_strobe),
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.reset (reset),
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.address (bus_address),
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.command (bus_command),
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.nibble_in (bus_nibble_in),
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.nibble_out (bus_nibble_out),
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.bus_error (bus_error)
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);
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initial
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begin
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$display("initializing clocks");
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clk2 = 0;
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clk3 = 0;
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en_bus_clk = 0;
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$display("initialize cycle counter");
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cycle_ctr = -1;
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instr_ctr = 0;
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$display("initializing bus_command");
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bus_command = `BUSCMD_NOP;
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$display("initializing busstate");
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next_cycle = `BUSCMD_LOAD_PC;
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$display("Initializing decstate");
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decstate = 0;
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$display("initializing control bits");
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decode_error = 0;
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debug_stop = 0;
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bus_load_pc = 1;
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en_bus_load_pc = 1;
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read_next_pc = 1;
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execute_cycle = 0;
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inc_pc = 0;
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alu_halt = 0;
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alu_requested_halt = 0;
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$display("should be initializing registers");
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hex_dec = `MODE_HEX;
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PC = 0;
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new_PC = 0;
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next_PC = 0;
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inst_start_PC = 0;
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rstk_ptr = 7;
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// $monitor("rst %b | CLK %b | CLK2 %b | CLK3 %b | PH0 %b | PH1 %b | PH2 %b | PH3 %b | CTR %d | EBCLK %b| STRB %b | BLPC %b | bnbi %b | bnbo %b | nb %b ",
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// reset, clk, clk2, clk3, ph0, ph1, ph2, ph3, cycle_ctr, en_bus_clk, strobe, bus_load_pc, bus_nibble_in, bus_nibble_out, nibble);
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// $monitor("CTR %d | EBCLK %b| B_STRB %b | EDCLK %b | D_STRB %b | BLPC %b | bnbi %b | bnbo %b | nb %b ",
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// cycle_ctr, en_bus_clk, bus_strobe, en_dec_clk, dec_strobe, bus_load_pc, bus_nibble_in, bus_nibble_out, nibble);
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// $monitor("BLPC %b | EBLPC %b",
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// bus_load_pc, en_bus_load_pc);
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//$monitor("NC %h", next_cycle);
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end
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//--------------------------------------------------------------------------------------------------
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//
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// clock generation
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//
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//--------------------------------------------------------------------------------------------------
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always @(posedge clk)
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if (!reset) clk2 <= !clk2;
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always @(negedge clk)
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clk3 <= !clk3 | reset;
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assign bus_ctrl_clk = clk & !reset;
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assign ph0 = clk & clk3 & !reset;
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assign ph1 = !clk & !clk2 & !reset;
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assign ph2 = clk & !clk3 & !reset;
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assign ph3 = !clk & clk2 & !reset;
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assign bus_strobe = ph1 & en_bus_clk;
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assign dec_strobe = ph3 & en_dec_clk;
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//--------------------------------------------------------------------------------------------------
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//
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// bus control
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//
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//--------------------------------------------------------------------------------------------------
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`include "fields.v"
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// `include "bus_commands.v"
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always @(posedge bus_ctrl_clk)
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begin
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if (!reset) begin
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if (clk3) begin
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en_dec_clk <= 0;
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cycle_ctr <= cycle_ctr + 1;
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case (next_cycle)
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`BUSCMD_NOP: begin
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bus_command <= `BUSCMD_NOP;
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$display("BUS NOT READING, STILL CLOCKING");
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end
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`BUSCMD_PC_READ: begin
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bus_command <= `BUSCMD_PC_READ;
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en_bus_clk <= 1;
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PC <= next_PC;
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inc_pc <= 1;
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end
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`BUSCMD_DP_READ: begin
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bus_command <= `BUSCMD_DP_READ;
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en_bus_clk <= 1;
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end
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`BUSCMD_DP_WRITE: begin
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bus_command <= `BUSCMD_DP_WRITE;
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bus_nibble_in <= nb_out;
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en_bus_clk <= 1;
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end
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`BUSCMD_LOAD_PC: begin
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bus_command <= `BUSCMD_LOAD_PC;
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bus_address <= new_PC;
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next_PC <= new_PC;
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PC <= new_PC;
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en_bus_clk <= 1;
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end
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`BUSCMD_LOAD_DP: begin
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bus_command <= `BUSCMD_LOAD_DP;
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bus_address <= add_out;
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en_bus_clk <= 1;
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end
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`BUSCMD_CONFIGURE: begin
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bus_command <= `BUSCMD_CONFIGURE;
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bus_address <= add_out;
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en_bus_clk <= 1;
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end
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`BUSCMD_RESET: begin
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bus_command <= `BUSCMD_RESET;
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en_bus_clk <= 1;
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end
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default: begin
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$display("BUS PHASE 1: %h UNIMPLEMENTED", next_cycle);
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end
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endcase
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end
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else begin
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case (next_cycle)
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`BUSCMD_NOP: begin
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en_dec_clk <= 1;
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end
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`BUSCMD_PC_READ: begin
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nb_in <= bus_nibble_out;
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en_dec_clk <= 1;
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if (inc_pc) begin
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next_PC <= PC + 1;
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inc_pc <= 0;
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end
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// $display("reading nibble %h", bus_nibble_out);
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end
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`BUSCMD_DP_READ: begin
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nb_in <= bus_nibble_out;
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en_dec_clk <= 1;
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end
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`BUSCMD_DP_WRITE: begin
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// $display("BUS PHASE 2: DP_WRITE cnt %h | ctr %h", t_cnt, t_ctr);
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en_dec_clk <= 1;
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end
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`BUSCMD_LOAD_PC: begin
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$display("CYCLE %d | INSTR %d -> BUSCMD_LOAD_PC %5h", cycle_ctr, instr_ctr, new_PC);
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en_dec_clk <= 1;
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end
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`BUSCMD_LOAD_DP: begin
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$display("CYCLE %d | INSTR %d -> BUSCMD_LOAD_DP %s %5h",
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cycle_ctr, instr_ctr, t_ptr?"D1":"D0", add_out);
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en_dec_clk <= 1;
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end
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`BUSCMD_CONFIGURE: begin
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$display("CYCLE %d | INSTR %d -> BUSCMD_CONFIGURE %5h", cycle_ctr, instr_ctr, add_out);
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en_dec_clk <= 1;
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end
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`BUSCMD_RESET: begin
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$display("CYCLE %d | INSTR %d -> BUSCMD_RESET", cycle_ctr, instr_ctr);
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en_dec_clk <= 1;
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end
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default: begin
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$display("BUS PHASE 2: %h UNIMPLEMENTED", next_cycle);
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end
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endcase
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en_bus_clk <= 0;
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end
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end
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else begin
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$display("RESET");
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end
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end
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always @(posedge ph1)
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begin
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end
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always @(posedge ph2) begin
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`include "decstates.v"
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`include "opcodes/z_alu_phase_2.v"
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end
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always @(posedge ph3) begin
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if (cycle_ctr == 260)
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debug_stop <= 1;
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end
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//--------------------------------------------------------------------------------------------------
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//
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// instruction decoder
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//
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//--------------------------------------------------------------------------------------------------
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`include "decstates.v"
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always @(posedge dec_strobe) begin
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if (alu_requested_halt) decode_error <= 1;
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if ((next_cycle == `BUSCMD_LOAD_PC)|
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(next_cycle == `BUSCMD_CONFIGURE)|
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(next_cycle == `BUSCMD_RESET)|
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((next_cycle == `BUSCMD_NOP)&
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(decstate == `DEC_START))) begin
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$display("SETTING next_cycle to BUSCMD_PC_READ");
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next_cycle <= `BUSCMD_PC_READ;
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end else begin
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`ifdef SIM
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if ((decstate == `DEC_START)|(decstate == `DEC_TEST_GO)) begin
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// display registers
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$display("PC: %05h Carry: %b h: %s rp: %h RSTK7: %05h", PC, Carry, hex_dec?"DEC":"HEX", rstk_ptr, RSTK[7]);
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$display("P: %h HST: %b ST: %b RSTK6: %5h", P, HST, ST, RSTK[6]);
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$display("A: %h R0: %h RSTK5: %5h", A, R0, RSTK[5]);
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$display("B: %h R1: %h RSTK4: %5h", B, R1, RSTK[4]);
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$display("C: %h R2: %h RSTK3: %5h", C, R2, RSTK[3]);
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$display("D: %h R3: %h RSTK2: %5h", D, R3, RSTK[2]);
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$display("D0: %h D1: %h R4: %h RSTK1: %5h", D0, D1, R4, RSTK[1]);
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$display(" RSTK0: %5h", RSTK[0]);
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end
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`endif
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$display("CYCLE %d | NEXTC %h | INSTR %d | PC %h | DECSTATE %3h | NIBBLE %h",
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cycle_ctr, next_cycle,
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(decstate == `DEC_START)?instr_ctr+1:instr_ctr,
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PC, decstate, nb_in);
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case (decstate)
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`DEC_START: begin
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instr_ctr <= instr_ctr + 1;
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inst_start_PC <= PC;
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case (nb_in)
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4'h0: decstate <= `DEC_0X;
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4'h1: decstate <= `DEC_1X;
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4'h2: decstate <= `DEC_P_EQ_N;
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4'h3: decstate <= `DEC_LC_LEN;
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4'h6: decstate <= `DEC_GOTO;
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4'h7: decstate <= `DEC_GOSUB;
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4'h8: decstate <= `DEC_8X;
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4'hA: begin
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fields_return <= `DEC_Axx_EXEC;
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decstate <= `DEC_ab_FIELDS;
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end
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4'hB: begin
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fields_return <= `DEC_Bxx_EXEC;
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decstate <= `DEC_ab_FIELDS;
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end
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4'hC: decstate <= `DEC_CX;
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4'hD: decstate <= `DEC_DX;
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4'hF: decstate <= `DEC_FX;
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default: begin
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$display("ERROR : DEC_START");
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decode_error <= 1;
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end
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endcase
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end
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`include "opcodes/0x.v"
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`include "opcodes/1x.v"
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`include "opcodes/13x_ptr_and_AC.v"
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`include "opcodes/1[45]_memaccess.v"
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`include "opcodes/1[678C]n_D[01]_math_n.v"
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`include "opcodes/1[ABEF]nnnnn_D[01]_EQ_5n.v"
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`include "opcodes/2n_P_EQ_n.v"
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`include "opcodes/3n[x...]_LC.v"
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`include "opcodes/6xxx_GOTO.v"
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`include "opcodes/7xxx_GOSUB.v"
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`include "opcodes/8x.v"
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`include "opcodes/80x.v"
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`include "opcodes/808x.v"
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`include "opcodes/808[4-B]_[AC]BIT_set_test.v"
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`include "opcodes/80[CD]n_C_and_P_n.v"
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`include "opcodes/82x_CLRHST.v"
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`include "opcodes/8[4567]n_work_test_ST.v"
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`include "opcodes/8[89]n_test_P.v"
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`include "opcodes/8Ax_test_[n]eq_A.v"
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`include "opcodes/8[DF]xxxxx_GO.v"
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`include "opcodes/A[ab]x.v"
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`include "opcodes/B[ab]x.v"
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`include "opcodes/Cx.v"
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`include "opcodes/Dx_regs_field_A.v"
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`include "opcodes/Fx.v"
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`include "opcodes/xx_RTNYES_GOYES.v"
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`include "opcodes/z_alu_phase_3.v"
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`include "opcodes/z_fields.v"
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default: begin
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$display("ERROR : GENERAL");
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decode_error <= 1;
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end
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endcase
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end
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end
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//--------------------------------------------------------------------------------------------------
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//
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// dump all registers on leds
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//
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//--------------------------------------------------------------------------------------------------
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`ifndef SIM
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`define REGDMP_HEX 0
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always @(negedge clk)
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begin
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case (regdump)
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`REGDMP_HEX: led <= {7'b0000000, hex_dec};
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default: led <= 8'b11111111;
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endcase
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regdump <= regdump + 1;
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if (reset)
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regdump <= `REGDMP_HEX;
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end
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`endif
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assign halt = bus_error | decode_error | debug_stop;
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// Verilator lint_off UNUSED
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//wire [N-1:0] unused;
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//assign unused = { };
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// Verilator lint_on UNUSED
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endmodule
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`ifdef SIM
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module saturn_tb;
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reg clk;
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reg reset;
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wire halt;
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wire [3:0] busstate;
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wire [11:0] decstate;
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saturn_core saturn (
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.clk (clk),
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.reset (reset),
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.halt (halt),
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.busstate (busstate),
|
|
.decstate (decstate)
|
|
);
|
|
|
|
always
|
|
#10 clk = (clk === 1'b0);
|
|
|
|
initial begin
|
|
//$monitor ("c %b | r %b | run %h | dec %h", clk, reset, runstate, decstate);
|
|
end
|
|
|
|
initial begin
|
|
$display("starting the simulation");
|
|
clk <= 0;
|
|
reset <= 1;
|
|
@(posedge clk);
|
|
@(posedge clk);
|
|
@(posedge clk);
|
|
reset <= 0;
|
|
@(posedge halt);
|
|
$finish;
|
|
end
|
|
|
|
|
|
endmodule
|
|
|
|
`else
|
|
|
|
|
|
`endif |