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https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
successfully handles the first 4 opcodes and bails out on error
This commit is contained in:
Raphael Jacquot
parent
17c2278c99
commit
9ecdc1799b
2 changed files with 71 additions and 19 deletions
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@ -8,10 +8,12 @@ module saturn_decoder(
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i_clk,
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i_reset,
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i_cycles,
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i_en_dbg,
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i_en_dec,
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i_en_exec,
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// i_stalled,
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i_nibble);
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i_nibble,
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o_dec_error);
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/*
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* module input / output ports
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@ -19,11 +21,14 @@ module saturn_decoder(
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input wire i_clk;
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input wire i_reset;
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input wire [31:0] i_cycles;
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input wire i_en_dbg;
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input wire i_en_dec;
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input wire i_en_exec;
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// input wire i_stalled;
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input wire [3:0] i_nibble;
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output reg o_dec_error;
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/*
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* state registers
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*/
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@ -33,7 +38,8 @@ wire instr_start;
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reg [31:0] instr_ctr;
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initial begin
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continue = 0;
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continue = 0;
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o_dec_error = 0;
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`ifdef SIM
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// $monitor({"i_clk %b | i_reset %b | i_cycles %d | i_en_dec %b | i_en_exec %b |",
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// " continue %b | instr_start %b | i_nibble %h"},
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@ -44,6 +50,19 @@ initial begin
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`endif
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end
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/*
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* debugger
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*
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*/
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always @(posedge i_clk) begin
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if (i_en_dbg) begin
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`ifdef SIM
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$display("blk0x %b | ins_rtn %b | xm %b | carry %b", block_0x, ins_rtn, xm, carry);
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`endif
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end
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end
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/*
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* handle the fist nibble decoding
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* that's pretty simple though, will get tougher later on :-)
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@ -55,18 +74,29 @@ assign instr_start = ~continue || i_reset;
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always @(posedge i_clk) begin
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if (i_reset) begin
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block_0x <= 0;
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block_0x <= 0;
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o_dec_error <= 0;
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end else begin
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if (i_en_dec)
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if (instr_start && i_en_dec) begin
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if (instr_start) begin
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`ifdef SIM
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$display("%d | %b | %b | first nibble", i_cycles, i_en_dec, i_en_exec);
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$display("%d | %b | %b | fn %h", i_cycles, i_en_dec, i_en_exec, i_nibble);
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`endif
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continue <= 1;
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// assign block regs
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block_0x <= (i_nibble == 4'h0);
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case (i_nibble)
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4'h0: block_0x <= 1;
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default: begin
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`ifdef SIM
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$display("first_nibble: nibble %h not handled", i_nibble);
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`endif
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o_dec_error <= 1;
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end
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endcase
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end else begin
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`ifdef SIM
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$display("%d | first_nibble: clear block_0x", i_cycles);
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`endif
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block_0x <= 0;
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end
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end
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@ -78,6 +108,8 @@ end
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*
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* 00 RTNSXM
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* 01 RTN
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* 02 RTNSC
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* 03 RTNCC
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*
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*/
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@ -101,15 +133,22 @@ always @(posedge i_clk) begin
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`endif
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block_0x <= 0;
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case (i_nibble)
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4'h0, 4'h1, 4'h2, 4'h3:
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ins_rtn <= 1;
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4'h0, 4'h1, 4'h2, 4'h3: ins_rtn <= 1;
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default: begin
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`ifdef SIM
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$display("block_0x: nibble %h not handled", i_nibble);
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`endif
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o_dec_error <= 1;
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end
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endcase
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set_xm <= (i_nibble == 4'h0);
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set_carry <= (i_nibble[3:1] == 1);
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carry_val <= (i_nibble[1] && i_nibble[0]);
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continue <= (i_nibble == 4'hE);
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end else begin
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`ifdef SIM
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$display("%d | block_0x: clearing rtn, xm, sc, cv", i_cycles);
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`endif
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ins_rtn <= 0;
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set_xm <= 0;
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set_carry <= 0;
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@ -127,15 +166,22 @@ end
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*
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*****************************************************************************/
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reg xm;
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reg carry;
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always @(posedge i_clk) begin
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if (i_reset)
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set_xm <= 0;
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else
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if (i_en_exec && ins_rtn) begin
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if (i_en_exec)
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if (ins_rtn) begin
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`ifdef SIM
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$display("RTN (XM: %b SC %b CV %b)", set_xm, set_carry, carry_val);
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$display("RTN (XM: %b SC %b CV %b)", set_xm, set_carry, carry_val);
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`endif
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end;
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xm <= set_xm?1:xm;
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carry <= set_carry?carry_val:carry;
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// do RTN things
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end
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end
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@ -57,6 +57,7 @@ reg [31:0] max_cycle;
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// state machine stuff
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wire halt;
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wire dec_error;
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// hp48_bus bus_ctrl (
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// .strobe (bus_strobe),
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@ -69,13 +70,15 @@ wire halt;
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// );
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saturn_decoder i_decoder (
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.i_clk (clk),
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.i_reset (reset),
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.i_cycles (cycle_ctr),
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.i_en_dec (en_inst_dec),
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.i_en_exec (en_inst_exec),
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.i_clk (clk),
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.i_reset (reset),
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.i_cycles (cycle_ctr),
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.i_en_dbg (en_debugger),
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.i_en_dec (en_inst_dec),
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.i_en_exec (en_inst_exec),
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// .i_stalled (stalled),
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.i_nibble (nibble_in)
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.i_nibble (nibble_in),
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.o_dec_error (dec_error)
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);
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initial
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@ -161,11 +164,14 @@ always @(posedge clk)
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// RTNCC
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6: nibble_in <= 0;
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7: nibble_in <= 3;
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// SETHEX
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8: nibble_in <= 0;
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9: nibble_in <= 4;
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// END
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8: clock_end <= 1;
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50: clock_end <= 1;
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endcase
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assign halt = clock_end;
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assign halt = clock_end || dec_error;
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// Verilator lint_off UNUSED
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