diff --git a/saturn-decoder.v b/saturn-decoder.v
index 9e68ecf..047d41d 100644
--- a/saturn-decoder.v
+++ b/saturn-decoder.v
@@ -8,10 +8,12 @@ module saturn_decoder(
      i_clk, 
      i_reset,
      i_cycles,
+     i_en_dbg,
      i_en_dec,
      i_en_exec,
     //  i_stalled,
-     i_nibble);
+     i_nibble,
+     o_dec_error);
 
 /*
  * module input / output ports
@@ -19,11 +21,14 @@ module saturn_decoder(
 input   wire        i_clk;
 input   wire        i_reset;
 input   wire [31:0] i_cycles;
+input   wire        i_en_dbg;
 input   wire        i_en_dec;
 input   wire        i_en_exec;
 // input   wire            i_stalled;
 input   wire [3:0]  i_nibble;
 
+output  reg         o_dec_error;
+
 /*
  * state registers
  */
@@ -33,7 +38,8 @@ wire        instr_start;
 reg [31:0]  instr_ctr;
 
 initial begin
-  continue = 0;
+  continue    = 0;
+  o_dec_error = 0;
 `ifdef SIM
   // $monitor({"i_clk %b | i_reset %b | i_cycles %d | i_en_dec %b | i_en_exec %b |",
   //          " continue %b | instr_start %b | i_nibble %h"}, 
@@ -44,6 +50,19 @@ initial begin
 `endif
 end
 
+/*
+ * debugger
+ *
+ */
+
+always @(posedge i_clk) begin
+  if (i_en_dbg) begin
+`ifdef SIM
+    $display("blk0x %b | ins_rtn %b | xm %b | carry %b", block_0x, ins_rtn, xm, carry);
+`endif
+  end
+end
+
 /*
  * handle the fist nibble decoding
  * that's pretty simple though, will get tougher later on :-)
@@ -55,18 +74,29 @@ assign instr_start = ~continue || i_reset;
 
 always @(posedge i_clk) begin
   if (i_reset) begin
-    block_0x <= 0;
+    block_0x    <= 0;
+    o_dec_error <= 0;
   end else begin
     if (i_en_dec)
-      if (instr_start && i_en_dec) begin
+      if (instr_start) begin
 `ifdef SIM
-        $display("%d | %b | %b | first nibble", i_cycles, i_en_dec, i_en_exec);
+        $display("%d | %b | %b | fn %h", i_cycles, i_en_dec, i_en_exec, i_nibble);
 `endif
         continue <= 1;
         // assign block regs
-        block_0x <= (i_nibble == 4'h0);
+        case (i_nibble) 
+        4'h0: block_0x <= 1;
+        default: begin
+`ifdef SIM
+          $display("first_nibble: nibble %h not handled", i_nibble);
+`endif
+          o_dec_error <= 1;
+        end
+        endcase
       end else begin
+`ifdef SIM
         $display("%d | first_nibble: clear block_0x", i_cycles);
+`endif
         block_0x <= 0;
       end
     end
@@ -78,6 +108,8 @@ end
  *
  * 00   RTNSXM
  * 01   RTN
+ * 02   RTNSC
+ * 03   RTNCC
  *
  */
 
@@ -101,15 +133,22 @@ always @(posedge i_clk) begin
 `endif
         block_0x <= 0;
         case (i_nibble)
-        4'h0, 4'h1, 4'h2, 4'h3:
-          ins_rtn <= 1;
+        4'h0, 4'h1, 4'h2, 4'h3: ins_rtn <= 1;
+        default: begin
+`ifdef SIM
+          $display("block_0x: nibble %h not handled", i_nibble);
+`endif
+          o_dec_error <= 1;
+        end
         endcase
         set_xm    <= (i_nibble == 4'h0);
         set_carry <= (i_nibble[3:1] == 1);
         carry_val <= (i_nibble[1] && i_nibble[0]);
         continue <= (i_nibble == 4'hE);
       end else begin
+`ifdef SIM
         $display("%d | block_0x: clearing rtn, xm, sc, cv", i_cycles);
+`endif
         ins_rtn <= 0;
         set_xm <= 0;
         set_carry <= 0;
@@ -127,15 +166,22 @@ end
  * 
  *****************************************************************************/
 
+reg     xm;
+reg     carry;
+
 always @(posedge i_clk) begin
   if (i_reset) 
     set_xm <= 0;
   else
-    if (i_en_exec && ins_rtn) begin
+    if (i_en_exec)
+      if (ins_rtn) begin
 `ifdef SIM
-      $display("RTN (XM: %b SC %b CV %b)", set_xm, set_carry, carry_val);
+        $display("RTN (XM: %b SC %b CV %b)", set_xm, set_carry, carry_val);
 `endif
-    end;
+        xm <= set_xm?1:xm;
+        carry <= set_carry?carry_val:carry;
+        // do RTN things
+      end
 end
 
 
diff --git a/saturn_core.v b/saturn_core.v
index 95e5935..523881a 100644
--- a/saturn_core.v
+++ b/saturn_core.v
@@ -57,6 +57,7 @@ reg	    [31:0]	max_cycle;
 
 // state machine stuff
 wire			halt;
+wire			dec_error;
 
 // hp48_bus bus_ctrl (
 // 	.strobe			(bus_strobe),
@@ -69,13 +70,15 @@ wire			halt;
 // );
 
 saturn_decoder i_decoder (
-	.i_clk		(clk),
-	.i_reset	(reset),
-	.i_cycles	(cycle_ctr),
-	.i_en_dec	(en_inst_dec),
-	.i_en_exec  (en_inst_exec),
+	.i_clk			(clk),
+	.i_reset		(reset),
+	.i_cycles		(cycle_ctr),
+	.i_en_dbg   	(en_debugger),
+	.i_en_dec		(en_inst_dec),
+	.i_en_exec  	(en_inst_exec),
 	// .i_stalled	(stalled),
-	.i_nibble	(nibble_in)
+	.i_nibble		(nibble_in),
+	.o_dec_error	(dec_error)
 );
 
 initial
@@ -161,11 +164,14 @@ always @(posedge clk)
 		// RTNCC
 		6:  nibble_in <= 0;
 		7:  nibble_in <= 3;
+		// SETHEX
+		8:  nibble_in <= 0;
+		9:  nibble_in <= 4;
 		// END
-		8:  clock_end <= 1;
+		50:  clock_end <= 1;
 		endcase
 
-assign halt = clock_end;
+assign halt = clock_end || dec_error;
 
 
 // Verilator lint_off UNUSED