Miroirs/hp-saturn
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Author SHA1 Message Date
Raphael Jacquot
cfd7603e96 we have signal ! 2019-03-03 18:22:48 +01:00
Raphael Jacquot
c04c770cba successfully got the saturn to startup on the ECP5 \o/ 2019-03-03 17:29:30 +01:00
Raphael Jacquot
bc25d4a61a cleanup blinky test 2019-03-03 16:18:30 +01:00
Raphael Jacquot
42e49caca3 cleanup of top 2019-03-03 15:59:02 +01:00
Raphael Jacquot
e192444f51 added a chaser to test the board 2019-03-03 15:46:21 +01:00
Raphaël Jacquot
6dd38500a8 add a counter to slow things down 2019-03-03 15:19:07 +01:00
Raphael Jacquot
ca29b542c3 there, a working compile shell script 2019-03-03 14:16:58 +01:00
Raphael Jacquot
531e0cab02 update compile file 2019-03-03 14:00:10 +01:00
Raphaël Jacquot
28a81503eb store current PC for the currently decoding instruction 2019-03-03 13:34:00 +01:00
Raphaël Jacquot
b58be38b10 connect debugger to leds 2019-03-03 13:33:32 +01:00
Raphael Jacquot
a6d5491619 fix the compilation for proper use of clk_25mhz signal as clock 2019-03-03 13:03:36 +01:00
Raphael Jacquot
9cb1618acb fix the rom module for proper bram generation 2019-03-03 13:03:12 +01:00
Raphaël Jacquot
391e5b6e93 change address bits to 12 (4096*4) 2019-03-03 10:27:31 +01:00
Raphael Jacquot
ae17cd1361 cleanup the rom 2019-03-03 10:24:53 +01:00
Raphaël Jacquot
2cab45a6ff remove the reset on the rom access, doesn't work 2019-03-03 10:08:26 +01:00
Raphael Jacquot
7e4ab90369 merge a few wire and assigns... can't do it on port declarations though 2019-03-03 09:47:28 +01:00
Raphael Jacquot
61957fab3e fix misplaced ifdef 
discover you can directly set contents of a wire without requiring an assign
 2019-03-03 09:43:18 +01:00
Raphaël Jacquot
eeb5150159 add the beginnings of a PC and RSTK handler 
fix bad maths in the rom-gx-r module
wire in the PC in the debugger and the control unit
add an execute flag, to start execution of partially
decoded instructions that need reading data from the
instruction stream
 2019-03-03 09:33:42 +01:00
Raphaël Jacquot
6c371cf203 increase ROMBITS to fully utilize one memory block 2019-03-03 08:09:33 +01:00
Raphael Jacquot
8fb7ad0eac try async version of reading rom... inconclusive 2019-03-03 08:03:43 +01:00
Raphaël Jacquot
3347a9702d add display of the carry 2019-03-03 07:45:03 +01:00
Raphael Jacquot
ff04360005 fix missing declaration 
fix driver conflict
 2019-03-03 07:31:18 +01:00
Raphaël Jacquot
b3d72c1d3b add some more debugging functionnality 
segregate reading of the rom in it's own little world
 2019-03-03 07:25:22 +01:00
Raphaël Jacquot
006b663147 implement hex->ascii conversion with a table 2019-03-03 06:57:14 +01:00
Raphael Jacquot
182623e043 remove char counting aid 2019-03-02 22:48:34 +01:00
Raphael Jacquot
21ad359673 fix compiling 
fix the way the bus controller program worked, which generated evil
inferred latches
 2019-03-02 22:33:58 +01:00
Raphaël Jacquot
42e8a146ce start implementing some type of debugging functionnality 2019-03-02 21:45:38 +01:00
Raphaël Jacquot
2fcd9f7b23 decode our first instruction 
execute said instruction
start implementing the debugging engine to see what we are doing
 2019-03-02 19:40:31 +01:00
Raphaël Jacquot
c75b33a64a update readme 2019-03-02 17:06:23 +01:00
Raphael Jacquot
c5355b4a90 enough was done to start feeding the decoder 2019-03-02 15:52:56 +01:00
Raphael Jacquot
cd2b74dcc8 add some commenting 2019-03-02 15:01:00 +01:00
Raphael Jacquot
3cbd6ac5e1 we are now up to reading the first instruction nibbles 2019-03-02 14:38:01 +01:00
Raphael Jacquot
8ce2d2a993 implement more of the bus controller 2019-03-02 13:22:09 +01:00
Raphael Jacquot
15f9b03321 remove product file 2019-02-25 09:51:51 +01:00
Raphael Jacquot
e761f984c8 implement the basic rom, and add a few things 2019-02-25 09:17:17 +01:00
Raphael Jacquot
8866b8c175 starts complete rewrite 2019-02-24 23:30:57 +01:00
Raphael Jacquot
570807cf61 time to start over, this this is broken beyond fiddling 2019-02-24 21:54:15 +01:00
Raphael Jacquot
49b20d72f3 restore RTN / RTNCC / RTNSC 2019-02-23 06:57:48 +01:00
Raphael Jacquot
7376c920bc change the clock phase generation from a counter to a shift register 
adapt everywhere needed
 2019-02-22 19:30:53 +01:00
Raphael Jacquot
8725b736b5 attempt to change things according to ylamarre 2019-02-22 18:38:09 +01:00
Raphael Jacquot
6126bddc90 C=P n and SETHEX / SETDEC 2019-02-22 16:49:06 +01:00
Raphael Jacquot
ebbea44c50 add clearing HST 2019-02-22 16:37:35 +01:00
Raphael Jacquot
390bdcd22f simplify things in the ALU 2019-02-22 15:48:11 +01:00
Raphael Jacquot
2028715939 implement PC related functionnality, relative and absolute jumps 2019-02-22 12:00:23 +01:00
Raphael Jacquot
93d786c2c1 alu rewrite in progress 2019-02-22 08:22:32 +01:00
Raphael Jacquot
93c856666e modify the alu to make it faster for certain operations. 2019-02-21 22:44:55 +01:00
Raphael Jacquot
7e6250f59b fix off-by-one error in write loop 2019-02-21 17:10:03 +01:00
Raphael Jacquot
30d7e6c8df entirely rework the DP_WRITE and WRITE_DP case 2019-02-21 16:55:08 +01:00
Raphael Jacquot
7d63f0f57a cleanups and move things around 2019-02-20 17:36:21 +01:00
Raphael Jacquot
70ddc7f9b6 cleanups of the bus controller (more to do) 2019-02-20 16:21:39 +01:00