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2019-02-23 06:57:48 +01:00
alu rework the clocking 2019-02-11 19:24:57 +01:00
.gitignore major changes in the fields decoder 2019-02-12 21:43:54 +01:00
compile add testing for yosys out status 2019-02-12 14:50:13 +01:00
dbg_const.v
dbg_module.v
def-alu.v nothing notable 2019-02-19 16:16:53 +01:00
def-buscmd.v start on the bus controller 2019-02-16 22:38:44 +01:00
def-clocks.v start implementing the bus controller 2019-02-17 08:35:26 +01:00
def-fields.v start handling ALU related stuff 2019-02-12 12:43:36 +01:00
empty_lfe5u-85f.config
gen_rom_hex.py
gxrom-r-decompile
history.txt entirely rework the DP_WRITE and WRITE_DP case 2019-02-21 16:55:08 +01:00
hp48_00_bus.v
hp48_01_io_ram.v
hp48_02_sys_ram.v
hp48_06_rom.v
ico
icoboard.pcf
Makefile
old_bus_controller.v major surgery in progress 2019-02-11 20:27:51 +01:00
old_regs.v major surgery in progress 2019-02-11 20:27:51 +01:00
README.md cleanup the simulated rom interface 2019-02-18 11:36:28 +01:00
rom-gx-r.hex
run.sh add clearing HST 2019-02-22 16:37:35 +01:00
saturn-core.ESP5.ys implement more instructions 2019-02-14 22:14:52 +01:00
saturn_alu.v restore RTN / RTNCC / RTNSC 2019-02-23 06:57:48 +01:00
saturn_bus_ctrl.v restore RTN / RTNCC / RTNSC 2019-02-23 06:57:48 +01:00
saturn_core.ICE40.ys
saturn_core.v restore RTN / RTNCC / RTNSC 2019-02-23 06:57:48 +01:00
saturn_decoder.v simplify things in the ALU 2019-02-22 15:48:11 +01:00
saturn_decoder_block_8.v simplify things in the ALU 2019-02-22 15:48:11 +01:00
saturn_decoder_block_vars.v simplify things in the ALU 2019-02-22 15:48:11 +01:00
saturn_decoder_debugger.v entirely rework the DP_WRITE and WRITE_DP case 2019-02-21 16:55:08 +01:00
saturn_decoder_fields.v add copyright and license (oops) 2019-02-20 09:15:22 +01:00
saturn_decoder_registers.v add clearing HST 2019-02-22 16:37:35 +01:00
saturn_test_rom.v restore RTN / RTNCC / RTNSC 2019-02-23 06:57:48 +01:00
testrom-2.hex modify the alu to make it faster for certain operations. 2019-02-21 22:44:55 +01:00
testrom.hex finished blocks 1, 2 and 3 2019-02-13 20:09:25 +01:00
text.vcd
ulx3s_v20.lpf

Verilog implementation of the HP saturn processor

licence: GPLv3 or later

timings: ___________
reset: |____________________________________________________ ____ ____ ____ ____ ____ ____ clk : | || || || || || |____ _________ _________ _________ _________ _________ counter: /0____X____1____X____2____X____3____X____0 _________ _________ phase_0: | || _________ phase_1: | |____ _________ phase_2: _______________| | _________ phase_3: ___________________________________| |

notes for using the ULX3S

Maybe linux ujprog won't find port because of insufficient priviledge. Either run ujprog as root or have udev rule:# this is for usb-serial tty device SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
MODE="664", GROUP="dialout" this is for ujprog libusb access

ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
GROUP="dialout", MODE="666"