Verilog implementation of the HP saturn processor

licence: GPLv3 or later

timings: ___________
reset: |____________________________________________________ ____ ____ ____ ____ ____ ____ clk : | || || || || || |____ _________ _________ _________ _________ _________ counter: /0____X____1____X____2____X____3____X____0 _________ _________ phase_0: | || _________ phase_1: | |____ _________ phase_2: _______________| | _________ phase_3: ___________________________________| |

notes for using the ULX3S

Maybe linux ujprog won't find port because of insufficient priviledge. Either run ujprog as root or have udev rule:# this is for usb-serial tty device SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
MODE="664", GROUP="dialout" this is for ujprog libusb access

ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
GROUP="dialout", MODE="666"