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Verilog 99%
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Raphaël Jacquot 391e5b6e93 change address bits to 12 (4096*4)
2019-03-03 10:27:31 +01:00
attic implement the basic rom, and add a few things 2019-02-25 09:17:17 +01:00
.gitignore fix compiling 2019-03-02 22:33:58 +01:00
compile fix compiling 2019-03-02 22:33:58 +01:00
empty_lfe5u-85f.config fix some verilator warnings 2019-02-04 20:36:47 +01:00
gen_rom_hex.py add licence info 2019-02-06 10:40:55 +01:00
ico implement more things, test with ice40 2019-02-10 12:04:53 +01:00
icoboard.pcf implement more things, test with ice40 2019-02-10 12:04:53 +01:00
make_saturn.ESP5.ys fix misplaced ifdef 2019-03-03 09:43:18 +01:00
make_saturn.ICE40.ys starts complete rewrite 2019-02-24 23:30:57 +01:00
Makefile implement ST=[01] n 2019-02-04 17:00:08 +01:00
README.md update readme 2019-03-02 17:06:23 +01:00
rom-gx-r.hex change the way the rom is encoded, makes things easier 2019-02-04 11:31:58 +01:00
run.sh add the beginnings of a PC and RSTK handler 2019-03-03 09:33:42 +01:00
saturn_bus.v implement the basic rom, and add a few things 2019-02-25 09:17:17 +01:00
saturn_bus_controller.v add the beginnings of a PC and RSTK handler 2019-03-03 09:33:42 +01:00
saturn_control_unit.v merge a few wire and assigns... can't do it on port declarations though 2019-03-03 09:47:28 +01:00
saturn_debugger.v add the beginnings of a PC and RSTK handler 2019-03-03 09:33:42 +01:00
saturn_def_alu.v start implementing some type of debugging functionnality 2019-03-02 21:45:38 +01:00
saturn_def_buscmd.v implement more of the bus controller 2019-03-02 13:22:09 +01:00
saturn_def_debugger.v add display of the carry 2019-03-03 07:45:03 +01:00
saturn_hp48gx_rom.v change address bits to 12 (4096*4) 2019-03-03 10:27:31 +01:00
saturn_inst_decoder.v add the beginnings of a PC and RSTK handler 2019-03-03 09:33:42 +01:00
saturn_regs_pc_rstk.v add the beginnings of a PC and RSTK handler 2019-03-03 09:33:42 +01:00
saturn_top.v fix compiling 2019-03-02 22:33:58 +01:00
ulx3s_v20.lpf commit more stuff 2019-02-04 17:14:08 +01:00
z_test_rom-1.hex time to start over, this this is broken beyond fiddling 2019-02-24 21:54:15 +01:00
z_test_rom-2.hex time to start over, this this is broken beyond fiddling 2019-02-24 21:54:15 +01:00

README.md

Verilog implementation of the HP saturn processor

licence: GPLv3 or later

timings:

           ___________   
reset:                |____________________________________________________
                ____      ____      ____      ____      ____      ____
clk :      ____|    |____|    |____|    |____|    |____|    |____|    |____
                          _________ _________ _________ _________ _________
counter:   ______________/____0____X____1____X____2____X____3____X____0____
                          _________                               _________
phase_0:   ______________|         |_____________________________|
                                    _________
phase_1:   ________________________|         |_____________________________
                                              _________
phase_2:   __________________________________|         |___________________
                                                        _________
phase_3:   ____________________________________________|         |_________

notes for using the ULX3S

Maybe linux ujprog won't find port because of insufficient priviledge. Either run ujprog as root or have udev rule:# this is for usb-serial tty device SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
MODE="664", GROUP="dialout" this is for ujprog libusb access

ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
GROUP="dialout", MODE="666"