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Author	SHA1	Message	Date
Raphael Jacquot	bc4342cc23	fixups	2019-02-12 14:49:33 +01:00
Raphael Jacquot	88620f217c	start handling ALU related stuff	2019-02-12 12:43:36 +01:00
Raphael Jacquot	bcb44743de	add required bits to decode fields tables	2019-02-12 11:22:55 +01:00
Raphael Jacquot	d7894d7963	add handling of fields_f table (no decode yet)	2019-02-12 08:56:15 +01:00
Raphael Jacquot	407b0c6d8d	implement jump to block_0Ex	2019-02-12 08:48:13 +01:00
Raphael Jacquot	3136a4c37b	added tentative decoder stall support	2019-02-12 08:21:32 +01:00
Raphael Jacquot	c7cc7f417b	refactor as it was getting too complicated ... secret seems to limit the levels of imbricated ifs... added SETHEX SETDEC RSTK=C C=RSTK	2019-02-12 07:48:25 +01:00
Raphael Jacquot	d4c67cf8fc	finally, something that is synthesizable !	2019-02-12 00:07:12 +01:00
Raphael Jacquot	9ecdc1799b	successfully handles the first 4 opcodes and bails out on error	2019-02-11 22:57:00 +01:00
Raphael Jacquot	17c2278c99	yay, decodes the first 4 opcodes \o/	2019-02-11 22:29:13 +01:00
Raphael Jacquot	21c09f0c5f	first iteration of decoder version 3 ;-)	2019-02-11 21:36:02 +01:00
Raphael Jacquot	c454fb8b97	test of new decoder structure	2019-02-11 21:29:04 +01:00
Raphael Jacquot	2c06ce0359	major surgery in progress	2019-02-11 20:27:51 +01:00
Raphael Jacquot	9b2f5fa41c	more clocking work	2019-02-11 19:49:22 +01:00
Raphael Jacquot	be83ee0eed	rework the clocking	2019-02-11 19:24:57 +01:00
Raphael Jacquot	6c41e73688	update clock timings	2019-02-11 16:58:15 +01:00
Raphael Jacquot	cbfbe4eb3f	renumber debug opcodes ... add add_cst and sub_cst alu opcodes port pointer math to use ALU make A[ab]x more readable	2019-02-11 15:36:51 +01:00
Raphael Jacquot	9799ea7618	use the ALU for 13x opcodes ... comment debug code add some debug code elsewhere	2019-02-11 13:17:18 +01:00
Raphael Jacquot	61bb45c54f	cleanup	2019-02-11 12:05:51 +01:00
Raphael Jacquot	b39c56a43c	make things more readable	2019-02-11 11:29:31 +01:00
Raphael Jacquot	8b63d25e8f	cleanups	2019-02-11 10:41:34 +01:00
Raphael Jacquot	6407e6673e	implement EXCH alu op	2019-02-11 10:29:22 +01:00
Raphael Jacquot	6d8924cf1d	clear alu_debug and dbg_op_code on each instruction start	2019-02-11 10:29:05 +01:00
Raphael Jacquot	046fa457be	add stuff for a future debugger	2019-02-11 09:13:16 +01:00
Raphael Jacquot	17b8b14db7	more fixes	2019-02-11 09:13:06 +01:00
Raphael Jacquot	6a1e9eff7e	various ALU fixage	2019-02-11 09:12:42 +01:00
Raphael Jacquot	0eeb018b56	move to using the ALU	2019-02-11 09:12:19 +01:00
Raphael Jacquot	9cd9c18381	add new registers	2019-02-11 09:11:40 +01:00
Raphael Jacquot	46890c6394	refactor ALU operations	2019-02-11 07:04:42 +01:00
Raphael Jacquot	d6a8bee3fe	add a register "comes from memory"	2019-02-11 07:03:55 +01:00
Raphael Jacquot	1799ac8eb6	remove DEC_LC_LEN -> DEC_LC	2019-02-11 07:03:37 +01:00
Raphael Jacquot	aa95324ea9	implement LC with ALU operations ... (need to find a way to output the instruction representation)	2019-02-11 07:03:20 +01:00
Raphael Jacquot	d6b59740dd	add Dn=(2)	2019-02-10 23:00:20 +01:00
Raphael Jacquot	43dd894888	more work on ALU	2019-02-10 23:00:06 +01:00
Raphael Jacquot	799fc3c327	convert stuff to use the ALU module instead	2019-02-10 22:02:39 +01:00
Raphael Jacquot	f21dcd8c23	add alu stuff	2019-02-10 18:46:26 +01:00
Raphael Jacquot	ec83140ff3	remove some stuff	2019-02-10 18:45:52 +01:00
Raphael Jacquot	c26772b4f9	implement RSTK=C	2019-02-10 13:57:30 +01:00
Raphael Jacquot	4e33d9c145	fix documentation comprehension error	2019-02-10 13:50:11 +01:00
Raphael Jacquot	efd93e4a95	add or substract constant do D0 and D1	2019-02-10 13:39:56 +01:00
Raphael Jacquot	bde3e1a027	add D0=(4) and transfer on field W	2019-02-10 12:47:50 +01:00
Raphael Jacquot	23a8e32e31	implement more things, test with ice40	2019-02-10 12:04:53 +01:00
Raphael Jacquot	4594dec086	more stuff implemented	2019-02-10 09:02:24 +01:00
Raphael Jacquot	71b2349831	lots of corrections	2019-02-09 19:18:58 +01:00
Raphael Jacquot	b0b3373e30	implement more versions of RTN	2019-02-09 12:03:43 +01:00
Raphael Jacquot	8fa16e6a1e	add more stuff	2019-02-09 11:53:45 +01:00
Raphael Jacquot	de5bfe83cc	implement loading into D1 too	2019-02-09 09:49:22 +01:00
Raphael Jacquot	8ae31087eb	bus access all rewritten	2019-02-09 09:32:29 +01:00
Raphael Jacquot	c0e4c0b20c	apply identical treatment for BRAM access	2019-02-09 01:13:57 +01:00
Raphael Jacquot	da4299fd19	reading and writing to the blockram should be in separate always blocks	2019-02-09 01:06:44 +01:00