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Verilog 99%
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Makefile 0.2%
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Raphael Jacquot da4299fd19 reading and writing to the blockram should be in separate always blocks
2019-02-09 01:06:44 +01:00
opcodes Implement reset 2019-02-09 00:01:48 +01:00
.gitignore fix some verilator warnings 2019-02-04 20:36:47 +01:00
bus_commands.v rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
compile try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
decstates.v add GOSUB 2019-02-08 23:59:36 +01:00
demo.blif try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
empty_lfe5u-85f.config fix some verilator warnings 2019-02-04 20:36:47 +01:00
fields.v rewrite in less spaghetti code style 2019-02-08 19:09:13 +01:00
gen_rom_hex.py add licence info 2019-02-06 10:40:55 +01:00
gxrom-r-decompile implement ST=[01] n 2019-02-04 17:00:08 +01:00
hp48_00_bus.v rename and change a lot of things 2019-02-09 00:02:09 +01:00
hp48_01_io_ram.v refactor access to the sysram array 2019-02-09 00:55:09 +01:00
hp48_02_sys_ram.v reading and writing to the blockram should be in separate always blocks 2019-02-09 01:06:44 +01:00
hp48_06_rom.v rename and change a lot of things 2019-02-09 00:02:09 +01:00
ico try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
icoboard.pcf try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
Makefile implement ST=[01] n 2019-02-04 17:00:08 +01:00
README separate reading instructions from reading data 2019-02-07 08:35:59 +01:00
rom-gx-r.hex change the way the rom is encoded, makes things easier 2019-02-04 11:31:58 +01:00
run rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
saturn_core.ESP5.ys try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
saturn_core.ICE40.ys try replacing all ifs with a case... yosys blows up too 2019-02-07 11:54:11 +01:00
saturn_core.v Implement reset 2019-02-09 00:01:48 +01:00
text.vcd implement ST=[01] n 2019-02-04 17:00:08 +01:00
ulx3s_v20.lpf commit more stuff 2019-02-04 17:14:08 +01:00

README 

Verilog implementation of the HP saturn processor

licence: GPLv3 or later


timings:

read:
                ____      ____      ____      ____      ____
clk :      ____|    |____|    |____|    |____|    |____|    |____
                _________
address:   ____|         |_______________________________________
                     _________
data:      _________|         |__________________________________
                          
read:      ______________|_______________________________________