Raphael Jacquot
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b96dcd717c
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cleanups
pipeline reading from the system ram
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2019-03-15 13:50:23 +01:00 |
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Raphael Jacquot
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194415a6ed
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cleanups
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2019-03-15 13:31:37 +01:00 |
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Raphael Jacquot
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2bde756bfe
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add the sysram module
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2019-03-15 12:26:26 +01:00 |
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Raphael Jacquot
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d1cb911c5c
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properly state when the mmio is unconfigured
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2019-03-15 12:26:09 +01:00 |
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Raphael Jacquot
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2d43dc67b7
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add the rest of the pointer registers loading instructions
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2019-03-15 12:25:47 +01:00 |
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Raphael Jacquot
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12f542441d
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pipeline rstk_ptr calculations for push
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2019-03-15 11:35:33 +01:00 |
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Raphael Jacquot
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e1aa24d006
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fix MHZ->MHz unit
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2019-03-15 11:29:27 +01:00 |
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Raphael Jacquot
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81860700c0
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add defaults to case, verilator complained
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2019-03-15 10:53:14 +01:00 |
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Raphael Jacquot
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7b64f3e297
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implement GOSUB (7xxx)
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2019-03-15 10:21:02 +01:00 |
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Raphael Jacquot
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e9e7a6a5f0
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add nice message for rom on CONFIGURE command
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2019-03-15 10:20:21 +01:00 |
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Raphael Jacquot
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175c1a48d0
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major surgery, add memory read and write back in
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2019-03-15 07:15:45 +01:00 |
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Raphael Jacquot
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f572107227
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add some timing to the compile script
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2019-03-15 07:15:26 +01:00 |
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Raphael Jacquot
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b3bc8cf327
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add a comment about potential slowness
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2019-03-15 07:13:38 +01:00 |
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Raphael Jacquot
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2a4d684d0e
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fis typo
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2019-03-15 07:13:20 +01:00 |
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Raphael Jacquot
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3932d6e1f5
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added the code for memory read & write, but it's not enabled yet
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2019-03-14 23:07:42 +01:00 |
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Raphael Jacquot
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a1b22269b2
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add mmio
fix rtn instructions
decode block 14x
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2019-03-14 22:20:03 +01:00 |
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Raphael Jacquot
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b2ae484450
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implement the ALU as it should be
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2019-03-14 21:47:05 +01:00 |
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Raphael Jacquot
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137d9b3b5a
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change compile script to optimize for 50Mhz
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2019-03-14 18:05:31 +01:00 |
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Raphael Jacquot
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a533e4ea37
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cleanup the startup procedure
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2019-03-14 17:52:03 +01:00 |
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Raphael Jacquot
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9c05be1152
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remove useless crud about the ULX3S
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2019-03-14 16:39:20 +01:00 |
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Raphael Jacquot
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c62d562008
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make it so that execution of bus programs happen
in the same cycle as the instruction
modify the way jump and rtn are handled
add some registers to the debugger
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2019-03-14 16:37:51 +01:00 |
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Raphael Jacquot
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e97ec2243f
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pipelining of reading from rom
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2019-03-14 14:33:28 +01:00 |
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Raphael Jacquot
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c30b96d1af
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fix an unused warning
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2019-03-14 13:49:38 +01:00 |
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Raphael Jacquot
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5f4a8ca8bd
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more fixes
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2019-03-14 13:47:09 +01:00 |
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Raphael Jacquot
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35823428e7
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other verilator fixes
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2019-03-14 13:45:14 +01:00 |
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Raphael Jacquot
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ef93420950
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first verilator error fixes
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2019-03-14 13:33:07 +01:00 |
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Raphael Jacquot
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d808e636c2
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add script to run verilator
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2019-03-14 13:32:50 +01:00 |
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Raphael Jacquot
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66bcb23d2c
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fix gitignore
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2019-03-14 13:22:15 +01:00 |
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Raphael Jacquot
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9549b53edc
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implement bus trasfers debugging
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2019-03-06 18:19:02 +01:00 |
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Raphael Jacquot
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6d940c7f95
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fix the conditions for the debugger to spew chars aout
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2019-03-06 14:41:18 +01:00 |
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Raphael Jacquot
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e09ed6bc28
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udate makefile
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2019-03-06 12:49:01 +01:00 |
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Raphaël Jacquot
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f86a1d03c5
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implement base alu functionnality
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2019-03-06 12:16:34 +01:00 |
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Raphael Jacquot
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98b3ed1b79
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decode Aax and Abx
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2019-03-05 07:56:33 +01:00 |
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Raphael Jacquot
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f12a74a917
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print a "." when the bus is active, but not reading
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2019-03-05 06:47:02 +01:00 |
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Raphaël Jacquot
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ddae7f9332
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start implementing block Axx
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2019-03-05 06:26:33 +01:00 |
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Raphaël Jacquot
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f3d1a4d9d4
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implement D0=(5)
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2019-03-05 06:14:38 +01:00 |
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Raphaël Jacquot
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28483afe9a
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implement CONFIG and RTN* (0[0-3])
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2019-03-05 05:39:34 +01:00 |
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Raphael Jacquot
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9168cbc1a2
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victory, this works on the fpga \o/
using "=" instead of "<=" is evil !
make the fpga halt when necessary
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2019-03-04 22:48:09 +01:00 |
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Raphael Jacquot
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4d578f8f18
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ok, we're getting somewhere
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2019-03-04 21:10:12 +01:00 |
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Raphaël Jacquot
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7e0f4a9c0f
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change the way clk_en is generated
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2019-03-04 19:59:00 +01:00 |
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Raphael Jacquot
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f502451548
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update debugger
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2019-03-04 19:15:44 +01:00 |
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Raphael Jacquot
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6964b72df1
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ok. serial sort of works, except it doesn't...
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2019-03-04 18:29:00 +01:00 |
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Raphael Jacquot
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6f3f3ce73c
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debug the seial port
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2019-03-04 17:01:59 +01:00 |
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Raphael Jacquot
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dc927031e4
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cleanups and simplifications
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2019-03-04 15:44:51 +01:00 |
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Raphael Jacquot
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ae164feb19
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there, serial port works at 115200
needed to add \r,..
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2019-03-04 15:24:05 +01:00 |
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Raphael Jacquot
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fcea35b4cb
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oops, LSB first
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2019-03-04 15:15:11 +01:00 |
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Raphael Jacquot
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5716904ac8
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add the serial port to the complie
change speed to 115200
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2019-03-04 14:53:48 +01:00 |
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Raphaël Jacquot
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7708d7a85c
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attached serial port tentative
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2019-03-04 14:40:31 +01:00 |
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Raphael Jacquot
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d87eb7786c
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add an extra script
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2019-03-04 13:44:37 +01:00 |
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Raphael Jacquot
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383841f89a
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make it yet faster
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2019-03-04 13:29:03 +01:00 |
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