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Author SHA1 Message Date
Raphael Jacquot
6bb654944f move the test rom to a separate module 2019-02-19 16:15:03 +01:00
Raphael Jacquot
4cce55e4ba initialize all registers, implement jmp_rel2 
cleanup the controller some more
prepare the core to be rewired
add support for block Bx
 2019-02-18 17:38:25 +01:00
Raphael Jacquot
4418ed5824 save one cycle on P= n 2019-02-18 11:36:39 +01:00
Raphael Jacquot
f660168393 cleanup the simulated rom interface 2019-02-18 11:36:28 +01:00
Raphael Jacquot
1444baca19 implement read from DP 2019-02-18 07:43:36 +01:00
Raphael Jacquot
0a45b014d7 moved main registers to arrays, makes things much simpler and better, it seems 2019-02-17 23:05:33 +01:00
Raphael Jacquot
01429b4493 tested all the way to cycle 400 where transfers from memory need to be fixed in the bus controller 2019-02-17 21:20:18 +01:00
Raphael Jacquot
5c4bff0b5e rewrite the messy hadling of load_dp and dp_write 2019-02-17 20:23:43 +01:00
Raphael Jacquot
0d3c3ecd3e implement CONFIG 
cleanup the bus controller
 2019-02-17 19:29:39 +01:00
Raphael Jacquot
7a3a36bd25 implement the reset bus command 2019-02-17 15:03:36 +01:00
Raphael Jacquot
1c719a1828 cleanup and reorganization for readability 2019-02-17 12:57:38 +01:00
Raphael Jacquot
8fc7cde507 implement the pieces to replicate the bus data transfers for writing data out. 2019-02-17 12:05:38 +01:00
Raphael Jacquot
128921c364 start implementing the bus controller 2019-02-17 08:35:26 +01:00
Raphael Jacquot
500e013bf5 start on the bus controller 2019-02-16 22:38:44 +01:00
Raphael Jacquot
781d15e0c7 hide some display instructions 2019-02-16 12:26:24 +01:00
Raphael Jacquot
ea3f53f70d implement calculations for # test 
modify calculations for the unconditional jump and reload PC condition
 2019-02-16 12:17:40 +01:00
Raphael Jacquot
06f79dca88 implemented decoding of 8Ax block, equality and inequality tests over 
field A. needs implementing the actual ALU op
implemented RTNYES/GOYES((not totally finished)
RTNYES works
need to find an actual GOYES to test that
 2019-02-16 11:08:34 +01:00
Raphael Jacquot
ef90d32971 handle block Cx 
add some code to handle goyes / rtnyes after the tests
 2019-02-16 07:35:06 +01:00
Raphael Jacquot
551b618098 fix driver conflicts 2019-02-15 17:23:07 +01:00
Raphael Jacquot
44ca0f4a15 fix driver conflict bug 
implement exch in ALU
fix jump base calculations
correct some things in debugger
fix fields and registers for some instructions
 2019-02-15 16:58:38 +01:00
Raphael Jacquot
3c44b2ae71 cleanup and a few renames 2019-02-15 11:55:58 +01:00
Raphael Jacquot
343f1e2247 separate block 8 as it's going to be rather large 2019-02-15 11:04:01 +01:00
Raphael Jacquot
25385115e0 separate the decoder in multiple files, it was becoming unwiedly ;-) 2019-02-15 10:47:00 +01:00
Raphael Jacquot
1f01d9bdb9 implement block Abx 2019-02-15 09:01:57 +01:00
Raphael Jacquot
4147a836d2 add stuff for memory transfers 2019-02-15 09:00:44 +01:00
Raphael Jacquot
e1f099145e add register 0 2019-02-15 09:00:00 +01:00
Raphael Jacquot
ff021e7618 add a feature to complain about not documented things 
start of handling Ax block
 2019-02-15 07:09:07 +01:00
Raphael Jacquot
235dbfa913 add some wires 2019-02-15 07:08:11 +01:00
Raphael Jacquot
8b985acc8a add setting HEX or DEC mode 
fix some cases not covered warnings
add handling of RTN instructions
 2019-02-15 07:07:55 +01:00
Raphael Jacquot
e72fe301b0 add some definitions for bits in HST register 2019-02-15 07:06:07 +01:00
Raphael Jacquot
96daffd25c implement CLRHST and friends 2019-02-14 22:54:54 +01:00
Raphael Jacquot
4b7e59fa21 implement more instructions 2019-02-14 22:14:52 +01:00
Raphael Jacquot
94ab98a175 remove old useless code 
fix some verilator reported bugs
 2019-02-14 15:27:17 +01:00
Raphael Jacquot
fd69407de0 alu coming up nicely, decoder gaining weight 2019-02-14 14:35:23 +01:00
Raphael Jacquot
f076cf6fb9 start the groundwork to implement jumps 
move PC handling into the ALU
 2019-02-14 08:59:04 +01:00
Raphael Jacquot
2e2d9108a8 the ALU machine seems to work 2019-02-13 23:18:50 +01:00
Raphael Jacquot
713e9b967b start implementing the ALU 2019-02-13 22:43:04 +01:00
Raphael Jacquot
aa1d8efd85 finished blocks 1, 2 and 3 2019-02-13 20:09:25 +01:00
Raphael Jacquot
c357160ab3 start memory transfers 2019-02-13 08:21:25 +01:00
Raphael Jacquot
2f813cc3a1 missing output in port 2019-02-13 00:19:47 +01:00
Raphael Jacquot
8858d08bb6 impement 1[012]x 2019-02-12 23:26:18 +01:00
Raphael Jacquot
466fabe58b major changes in the fields decoder 2019-02-12 21:43:54 +01:00
Raphael Jacquot
3fad39756f make more wires to remove if levels 2019-02-12 17:29:13 +01:00
Raphael Jacquot
1f66e782c1 hack in some wires to make things faster 2019-02-12 16:06:13 +01:00
Raphael Jacquot
eef2d13c60 add the block to setup registers for 0Efx 2019-02-12 15:33:04 +01:00
Raphael Jacquot
e409021f35 need more registers ;-) 2019-02-12 15:12:19 +01:00
Raphael Jacquot
bb633d5b80 work on more instructions 
set fields / registers
 2019-02-12 14:51:00 +01:00
Raphael Jacquot
13e390e8a6 add a few registers 2019-02-12 14:50:24 +01:00
Raphael Jacquot
81f859eb5d add testing for yosys out status 2019-02-12 14:50:13 +01:00
Raphael Jacquot
115d3a2544 add instructions to test 2019-02-12 14:49:53 +01:00