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117 commits 1 branch 0 tags 2 MiB
Verilog 99%
Shell 0.7%
Makefile 0.2%
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Raphael Jacquot c357160ab3 start memory transfers
2019-02-13 08:21:25 +01:00
alu rework the clocking 2019-02-11 19:24:57 +01:00
opcodes renumber debug opcodes 2019-02-11 15:36:51 +01:00
.gitignore major changes in the fields decoder 2019-02-12 21:43:54 +01:00
bus_commands.v rename runstates and starts splitting things up 2019-02-07 06:29:47 +01:00
compile add testing for yosys out status 2019-02-12 14:50:13 +01:00
dbg_const.v renumber debug opcodes 2019-02-11 15:36:51 +01:00
dbg_module.v add stuff for a future debugger 2019-02-11 09:13:16 +01:00
decstates.v remove DEC_LC_LEN -> DEC_LC 2019-02-11 07:03:37 +01:00
def-alu.v start memory transfers 2019-02-13 08:21:25 +01:00
def-fields.v start handling ALU related stuff 2019-02-12 12:43:36 +01:00
empty_lfe5u-85f.config fix some verilator warnings 2019-02-04 20:36:47 +01:00
gen_rom_hex.py add licence info 2019-02-06 10:40:55 +01:00
gxrom-r-decompile implement ST=[01] n 2019-02-04 17:00:08 +01:00
history.txt start memory transfers 2019-02-13 08:21:25 +01:00
hp48_00_bus.v bus access all rewritten 2019-02-09 09:32:29 +01:00
hp48_01_io_ram.v add more stuff 2019-02-09 11:53:45 +01:00
hp48_02_sys_ram.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
hp48_06_rom.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
ico implement more things, test with ice40 2019-02-10 12:04:53 +01:00
icoboard.pcf implement more things, test with ice40 2019-02-10 12:04:53 +01:00
Makefile implement ST=[01] n 2019-02-04 17:00:08 +01:00
old_bus_controller.v major surgery in progress 2019-02-11 20:27:51 +01:00
old_intruction_decoder.v major surgery in progress 2019-02-11 20:27:51 +01:00
old_regs.v major surgery in progress 2019-02-11 20:27:51 +01:00
README rework the clocking 2019-02-11 19:24:57 +01:00
rom-gx-r.hex change the way the rom is encoded, makes things easier 2019-02-04 11:31:58 +01:00
run add required bits to decode fields tables 2019-02-12 11:22:55 +01:00
saturn-alu.v remove debug line 2019-02-12 14:49:43 +01:00
saturn-core.ESP5.ys add required bits to decode fields tables 2019-02-12 11:22:55 +01:00
saturn-core.v fixups 2019-02-12 14:49:33 +01:00
saturn-decoder.v start memory transfers 2019-02-13 08:21:25 +01:00
saturn_core.ICE40.ys implement more things, test with ice40 2019-02-10 12:04:53 +01:00
testrom.hex start memory transfers 2019-02-13 08:21:25 +01:00
text.vcd implement ST=[01] n 2019-02-04 17:00:08 +01:00
ulx3s_v20.lpf commit more stuff 2019-02-04 17:14:08 +01:00

README 

Verilog implementation of the HP saturn processor

licence: GPLv3 or later


timings:
           ___________   
reset:                |____________________________________________________
                ____      ____      ____      ____      ____      ____
clk :      ____|    |____|    |____|    |____|    |____|    |____|    |____
                          _________ _________ _________ _________ _________
counter:   ______________/____0____X____1____X____2____X____3____X____0____
                          _________                               _________
phase_0:   ______________|         |_____________________________|
                                    _________
phase_1:   ________________________|         |_____________________________
                                              _________
phase_2:   __________________________________|         |___________________
                                                        _________
phase_3:   ____________________________________________|         |_________