Miroirs/hp-saturn
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295 commits 1 branch 0 tags 2 MiB
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31 commits

Author SHA1 Message Date
Raphael Jacquot
6fcf04a5c0 fix bus debugger for read program 2019-03-18 07:33:52 +01:00
Raphael Jacquot
c48944623d implement RTN 2019-03-15 21:38:28 +01:00
Raphael Jacquot
1771536ca0 implement block_15x 2019-03-15 20:42:51 +01:00
Raphael Jacquot
c953bc82f4 add block Cx and Fx 
implement 2CMPL and ADD
 2019-03-15 17:17:19 +01:00
Raphael Jacquot
b96dcd717c cleanups 
pipeline reading from the system ram
 2019-03-15 13:50:23 +01:00
Raphael Jacquot
2bde756bfe add the sysram module 2019-03-15 12:26:26 +01:00
Raphael Jacquot
12f542441d pipeline rstk_ptr calculations for push 2019-03-15 11:35:33 +01:00
Raphael Jacquot
175c1a48d0 major surgery, add memory read and write back in 2019-03-15 07:15:45 +01:00
Raphael Jacquot
a1b22269b2 add mmio 
fix rtn instructions
decode block 14x
 2019-03-14 22:20:03 +01:00
Raphael Jacquot
b2ae484450 implement the ALU as it should be 2019-03-14 21:47:05 +01:00
Raphael Jacquot
e97ec2243f pipelining of reading from rom 2019-03-14 14:33:28 +01:00
Raphaël Jacquot
f86a1d03c5 implement base alu functionnality 2019-03-06 12:16:34 +01:00
Raphaël Jacquot
f3d1a4d9d4 implement D0=(5) 2019-03-05 06:14:38 +01:00
Raphaël Jacquot
28483afe9a implement CONFIG and RTN* (0[0-3]) 2019-03-05 05:39:34 +01:00
Raphael Jacquot
4d578f8f18 ok, we're getting somewhere 2019-03-04 21:10:12 +01:00
Raphael Jacquot
6f3f3ce73c debug the seial port 2019-03-04 17:01:59 +01:00
Raphaël Jacquot
7708d7a85c attached serial port tentative 2019-03-04 14:40:31 +01:00
Raphaël Jacquot
479382e004 export rstk_ptr to debugger 
implement LCHEX (and almost done for LAHEX)
 2019-03-04 13:28:08 +01:00
Raphaël Jacquot
e47f12f1d7 implement push PC to RSTK 2019-03-04 11:52:05 +01:00
Raphaël Jacquot
908b96df6f implement CLRHST and variants 
implement SET[HEX|DEC]
 2019-03-04 10:53:37 +01:00
Raphaël Jacquot
735504d2b3 implement RESET instruction 2019-03-04 10:15:37 +01:00
Raphaël Jacquot
18a56d750b export main registers to debugger 
add C register
implement C=P n
add dumping C register
 2019-03-04 09:58:13 +01:00
Raphael Jacquot
b2811e82eb too shlow now 
bus halt in simulation only
 2019-03-04 08:44:05 +01:00
Raphael Jacquot
12173e72c4 fix forgotten reset 
slow it down some
 2019-03-04 08:32:34 +01:00
Raphaël Jacquot
e0eecde066 merge 2019-03-04 08:10:53 +01:00
Raphaël Jacquot
009f01f5d7 implement 8[45]x ST=[01] n 
implement GOVLNG
dump 2 lines of registers in debugger now
 2019-03-04 08:08:02 +01:00
Raphael Jacquot
8cbf9f59a2 make the blinkenlights pretty 2019-03-03 23:24:50 +01:00
Raphaël Jacquot
6dd38500a8 add a counter to slow things down 2019-03-03 15:19:07 +01:00
Raphaël Jacquot
b58be38b10 connect debugger to leds 2019-03-03 13:33:32 +01:00
Raphael Jacquot
e761f984c8 implement the basic rom, and add a few things 2019-02-25 09:17:17 +01:00
Raphael Jacquot
8866b8c175 starts complete rewrite 2019-02-24 23:30:57 +01:00