mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-27 09:58:16 +01:00
163 lines
No EOL
4.4 KiB
Verilog
163 lines
No EOL
4.4 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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module saturn_bus (
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i_clk,
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i_clk_en,
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i_reset,
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o_halt,
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o_phase,
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o_cycle_ctr,
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o_char_to_send
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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output wire [0:0] o_halt;
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output wire [1:0] o_phase;
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output wire [31:0] o_cycle_ctr;
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output wire [7:0] o_char_to_send;
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assign o_phase = phase;
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assign o_cycle_ctr = cycle_ctr;
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/**************************************************************************************************
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*
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* this is the main firmware rom module
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* this module is always active, there is no configuration.
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*
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*************************************************************************************************/
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saturn_hp48gx_rom hp48gx_rom (
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.i_clk (i_clk),
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.i_clk_en (i_clk_en),
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.i_reset (i_reset),
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.i_phase (phase),
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.i_cycle_ctr (cycle_ctr),
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.i_bus_clk_en (bus_clk_en),
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.i_bus_is_data (ctrl_bus_is_data),
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.o_bus_nibble_out (rom_bus_nibble_out),
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.i_bus_nibble_in (ctrl_bus_nibble_out)
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);
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wire [3:0] rom_bus_nibble_out;
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/**************************************************************************************************
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*
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* the main processor is hidden behind this bus controller device
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*
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*
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*************************************************************************************************/
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saturn_bus_controller bus_controller (
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.i_clk (i_clk),
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.i_clk_en (i_clk_en),
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.i_reset (i_reset),
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.i_phases (phases),
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.i_phase (phase),
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.i_cycle_ctr (cycle_ctr),
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.o_bus_clk_en (ctrl_bus_clk_en),
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.o_bus_is_data (ctrl_bus_is_data),
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.o_bus_nibble_out (ctrl_bus_nibble_out),
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.i_bus_nibble_in (ctrl_bus_nibble_in),
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// more ports should show up to allow for output to the serial port of debug information
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.o_debug_cycle (dbg_debug_cycle),
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.o_char_to_send (o_char_to_send),
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.o_halt (ctrl_halt)
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);
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wire [0:0] ctrl_bus_clk_en;
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wire [0:0] ctrl_bus_is_data;
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wire [3:0] ctrl_bus_nibble_out;
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reg [3:0] ctrl_bus_nibble_in;
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wire [0:0] dbg_debug_cycle;
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wire [0:0] ctrl_halt;
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/**************************************************************************************************
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*
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* priority logic for the bus
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*
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*
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*************************************************************************************************/
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reg [0:0] bus_halt;
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reg [3:0] phases;
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reg [1:0] phase;
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reg [31:0] cycle_ctr;
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wire [0:0] bus_clk_en = i_clk_en && ctrl_bus_clk_en;
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initial begin
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bus_halt = 1'b0;
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phases = 4'b1;
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cycle_ctr = 32'd0;
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end
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assign o_halt = bus_halt || ctrl_halt;
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/* handles modules priority
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* goes through all modules
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* if the module is active, this is the one giving out it's data
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* the last active module wins
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*/
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always @(*) begin
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ctrl_bus_nibble_in = rom_bus_nibble_out;
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end
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always @(*) begin
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phase = 2'd0;
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if (phases[1]) phase = 2'd1;
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if (phases[2]) phase = 2'd2;
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if (phases[3]) phase = 2'd3;
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end
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always @(posedge i_clk) begin
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/* if we're not debugging, advance phase on each clock */
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if (!dbg_debug_cycle && i_clk_en) begin
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phases <= {phases[2:0], phases[3]};
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/* using phases[3] here becase it will be phase_0 on the next step,
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* so we get to a new cycle on the first phase...
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*/
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cycle_ctr <= cycle_ctr + {31'b0, phases[3]};
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end
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`ifdef SIM
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if (cycle_ctr == 85) begin
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bus_halt <= 1'b1;
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$display("BUS %0d: [%d] enough cycles for now", phase, cycle_ctr);
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end
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`endif
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if (i_reset) begin
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bus_halt <= 1'b0;
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phases <= 4'b1;
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cycle_ctr <= 32'd0;
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end
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end
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endmodule |